URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 486

Rev 477, 2011-01-15 05:48:25 GMT
Author: julius
Log message:
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each.

Path
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S