OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] - Rev 363

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 363, 2010-09-12 07:57:53 GMT
  • Author: julius
  • Log message:
    ORPSoC's RTL code fixed to pass linting by Verilator.

    ORPSoC's debug interface disabled for now in both RTL and System C top level.

    Profiled building of cycle-accurate model now done correctly.
Path
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
/openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v
/openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_lsu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v
/openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sw/dhry/Makefile

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.