OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 354

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 354, 2010-09-08 18:00:48 GMT
  • Author: julius
  • Log message:
    Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

    * sw/support/crt0.S: Tick timer interrupt to increment variable
    now in place instead of calling customisable
    interrupt vector handler

    Changed all system frequencies in design to 50MHz.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.