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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 354
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Last modification
- Rev 354, 2010-09-08 18:00:48 GMT
- Author: julius
- Log message:
- Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler
Changed all system frequencies in design to 50MHz.
