URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] - Rev 40

Rev 40, 2009-06-09 09:18:09 GMT
Author: julius
Log message:
Added GDB server to verilog simulation via VPI and make target to build and run this model

Path
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/bench/verilog/vpi
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.h
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/jp_vpi.c
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/Makefile
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-vpi.h
/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog
/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v
/openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v
/openrisc/trunk/orpsocv2/sim/bin/icarus.scr
/openrisc/trunk/orpsocv2/sim/bin/Makefile