URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 354, 2010-09-08 18:00:48 GMT
• Author: julius

• Log message:

  Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
  
  * sw/support/crt0.S: Tick timer interrupt to increment variable
  now in place instead of calling customisable
  interrupt vector handler
  
  Changed all system frequencies in design to 50MHz.

Path
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v
/openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg
/openrisc/trunk/orpsocv2/sw/dhry/dhry.c
/openrisc/trunk/orpsocv2/sw/dhry/dhry.h
/openrisc/trunk/orpsocv2/sw/dhry/Makefile
/openrisc/trunk/orpsocv2/sw/include/board.h
/openrisc/trunk/orpsocv2/sw/include/dhry.h
/openrisc/trunk/orpsocv2/sw/or1200/or1200-simple.c
/openrisc/trunk/orpsocv2/sw/support/crt0.S