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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] - Rev 425

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Last modification

  • Rev 425, 2010-11-16 23:49:00 GMT
  • Author: julius
  • Log message:
    ORPSoC update:

    GDB servers in VPI and System C model updated to deal with
    packets gdb-7.2 sends.

    Documentation updated.

    Reference design tests can now be run in or1ksim (added rule
    to sim/bin/Makefile). or1200-except doesn't appear to work
    as illegal instruction error isn't causing jump to vector.

    Updated Or1200 tests to report test success value and then
    exit with value 0.
Path
/openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
/openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/README
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
/openrisc/trunk/orpsocv2/doc/orpsoc.texi
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg
/openrisc/trunk/orpsocv2/sw/apps/testfloat/fail.c
/openrisc/trunk/orpsocv2/sw/apps/testfloat/random.c
/openrisc/trunk/orpsocv2/sw/apps/testfloat/testfloat.c
/openrisc/trunk/orpsocv2/sw/apps/testfloat/testFunction.c
/openrisc/trunk/orpsocv2/sw/apps/testfloat/testLoops.c
/openrisc/trunk/orpsocv2/sw/apps/testfloat/testsoftfloat.c
/openrisc/trunk/orpsocv2/sw/apps/testfloat/writeHex.c
/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
/openrisc/trunk/orpsocv2/sw/Makefile.inc
/openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-maci.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S

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