OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] - Rev 544

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 544, 2011-05-25 09:37:59 GMT
  • Author: julius
  • Log message:
    ORPSoC ordb1a3pe1500 update - adding SD card controller.
Path
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsoccpuexpio.mkpinassigns
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_dbus.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/clkgen/clkgen.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/sd_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sdc_controller.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_bd.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_clock_divider.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_cmd_master.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_cmd_serial_host.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_controller_wb.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_crc_7.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_crc_16.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_data_master.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_data_serial_host.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_fifo_rx_filler.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_fifo_tx_filler.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_rx_fifo.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_rx_fifo_tb.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/sdc_controller/sd_tx_fifo.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.