OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] - Rev 409

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 409, 2010-11-03 13:14:32 GMT
  • Author: julius
  • Log message:
    ORPSoC: Renamed eth core to ethmac (correct name), added drivers for it.
    Updated ethernet MAC's instantiation in ORDB1A3PE1500 board build.
    Updated documentation.
Path
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/eth_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/doc/orpsoc.texi
/openrisc/trunk/orpsocv2/rtl/verilog/eth
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_register.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/README
/openrisc/trunk/orpsocv2/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v
/openrisc/trunk/orpsocv2/sw/drivers/ethmac
/openrisc/trunk/orpsocv2/sw/drivers/ethmac/ethmac.c
/openrisc/trunk/orpsocv2/sw/drivers/ethmac/include
/openrisc/trunk/orpsocv2/sw/drivers/ethmac/include/eth-phy-mii.h
/openrisc/trunk/orpsocv2/sw/drivers/ethmac/include/ethmac.h
/openrisc/trunk/orpsocv2/sw/drivers/ethmac/Makefile
/openrisc/trunk/orpsocv2/sw/tests/eth
/openrisc/trunk/orpsocv2/sw/tests/ethmac
/openrisc/trunk/orpsocv2/sw/tests/ethmac/board/eth-phy-mii.h
/openrisc/trunk/orpsocv2/sw/tests/ethmac/board/eth-ping.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/board/open-eth.h
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/eth-rx.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/eth-rxtx.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/eth-tx.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.