URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [include/] - Rev 502

Rev 502, 2011-03-11 18:47:48 GMT
Author: julius
Log message:
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default

Path
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/uart_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cy.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ov.S