URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 439, 2010-12-06 15:22:50 GMT
• Author: julius

• Log message:

  ORPSoC update
  
  Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
  Ethernet MAC FIFO synthesis issues with Xilinx XST
  
  Multiply/divide tests for to run on target.
  
  Added third interface to ram_wb module, changed reference design RAM to ram_wb
  wrapper. Updated verilog and system C monitor modules accordingly.
  
  Added ability to use ram_wb as internal memory on ML501 design.
  
  Fixed ethernet MAC tests for ML501.

Path
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile
/openrisc/trunk/orpsocv2/doc/orpsoc.texi
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb.v
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
/openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c
/openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-div.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mul.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interruptloopback.c