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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [rtl/] [verilog/] [versatile_mem_ctrl/] - Rev 408

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Last modification

  • Rev 408, 2010-11-03 00:57:09 GMT
  • Author: julius
  • Log message:
    ORPSoC update - adding support for ORSoC development board, many changes, documentation update, too.
Path
/openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v
/openrisc/trunk/orpsocv2/bench/verilog/include/eth_phy_defines.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/directControl_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/dpMem_dc_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/endpMux_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/fifoMux_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/fifoRTL_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/getPacket_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/HCTxPortArbiter_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostcontroller_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostSlaveMuxBI_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostSlaveMux_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/lineControlUpdate_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processRxBit_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processRxByte_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processTxByte_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/readUSBWireData_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/RxfifoBI_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/RxFifo_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/rxStatusMonitor_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SCTxPortArbiter_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/sendPacketArbiter_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/sendPacketCheckPreamble_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/sendPacket_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SIEReceiver_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SIETransmitter_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slavecontroller_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveDirectControl_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveGetPacket_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveRxStatusMonitor_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveSendPacket_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SOFController_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SOFTransmit_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/speedCtrlMux_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/TxfifoBI_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/TxFifo_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/updateCRC5_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/updateCRC16_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbConstants_h.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/USBHostControlBI_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbHostControl_h.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbHostControl_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbHostSlave_h.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbhostslave_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbhost_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSerialInterfaceEngine_h.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSerialInterfaceEngine_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/USBSlaveControlBI_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_h.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbslave_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/USBTxWireArbiter_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usb_hostslave_tb.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usb_slave_tb.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/wb_master_model.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/wishBoneBI_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/wishBoneBus_h.v
/openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/writeUSBWireData_simlib.v
/openrisc/trunk/orpsocv2/bench/verilog/wiredelay.v
/openrisc/trunk/orpsocv2/boards/actel
/openrisc/trunk/orpsocv2/boards/actel/backend
/openrisc/trunk/orpsocv2/boards/actel/backend/rtl
/openrisc/trunk/orpsocv2/boards/actel/backend/rtl/verilog
/openrisc/trunk/orpsocv2/boards/actel/backend/rtl/verilog/proasic3.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsoccpuboard.mkpins
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsoccpuexpio.mkpinassigns
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsocexpboard.mkpins
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/README
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/run
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/run/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/eth_pll.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/gbuf.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/orpsoc_flashROM.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal25_wb20.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal25_wb24.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb16.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb20.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb24.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb30.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/README
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/reset_buffer.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/orpsoc-testbench-defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/synthesis-defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/timescale.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/spi_slave.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_bytebus.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_dbus.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_ibus.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/README
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/clkgen
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/clkgen/clkgen.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/flashrom
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/flashrom/flashrom.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/flashrom/README
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/gpio.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/README
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/dbg_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/eth_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/i2c_master_slave_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/tap_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/uart_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_constants_h.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_hostcontrol_h.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_hostslave_h.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_serialinterfaceengine_h.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_slavecontrol_h.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_wishbonebus_h.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/README
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/burst_length_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/cke_delay_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/codec.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/copyright.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ctrl_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/dcm_pll.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_16.fzm
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_16_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_ff.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/delay.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/egress_fifo.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_adr_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_fill.fzm
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fizzim.pl
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fsm_sdr_16.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fsm_wb.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/inc_adr.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/latency_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/pre_delay_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_delay_counter_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16.fzm
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ddr.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_defines.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ip.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_top.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_wb.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/versatile_mem_ctrl.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/out
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/run
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/bootrom.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include/usbhostslave-host.h
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include/usbhostslave-slave.h
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/usbhostslave-host.c
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/usbhostslave-slave.c
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim/i2c_master_slave-loopback.c
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim/Makefile
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave
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/openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile
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