OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [syn/] - Rev 411

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 411, 2010-11-04 13:09:21 GMT
  • Author: julius
  • Log message:
    Improved ethmac testbench and software.

    Renamed some OR1200 library functions to be more generic.

    Fixed bug with versatile_mem_ctrl for Actel board.

    Added ability to simulate gatelevel modules alongside RTL modules
    in board build.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.