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  • Rev 677, 2012-02-21 16:01:04 GMT
  • Author: stekern
  • Log message:
    atlys: add 2-clock synchronizer chain for ddr2_calib_done

    The signal ddr2_calib_done signal comes from the ddr2 clock domain,
    while wb_req is treating it as if it came from wb_clk domain. As a
    result the timing analysis tool assumed a worst case scenario of 5ns
    between the two domains and the results were miserable.

    While we can argue that this is a multi-cycle path, the fact is that
    ddr2_calib_done feeds into multiple logic sinks and can potentially
    cause meta-stability issue in the design. The solution is to add a
    2-clock meta-stability filter to address both the timing problems and
    the meta-stability concern.

    Signed-off-by: Jason Zheng <jxzheng@gmail.com>
    Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
    Acked-by: Olof Kindgren <olof.kindgren@orsoc.se>

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