OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [bench/] [verilog/] - Rev 485

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 485, 2011-02-04 09:33:38 GMT
  • Author: julius
  • Log message:
    ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501
Path
/openrisc/trunk/orpsocv2/bench/verilog/include/or1200_monitor_defines.v
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h
/openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rx.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtx.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-tx.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile
/openrisc/trunk/orpsocv2/doc/orpsoc.texi
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sw/board/include/board.h
/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
/openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c
/openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c
/openrisc/trunk/orpsocv2/sw/lib/include/printf.h
/openrisc/trunk/orpsocv2/sw/lib/printf.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/utils/marksec
/openrisc/trunk/orpsocv2/sw/utils/merge2srec

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.