OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [rtl/] [verilog/] [gpio/] - Rev 486

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 412, 2010-11-05 01:00:58 GMT
  • Author: julius
  • Log message:
    ORPSoC update - Rearranged Xilinx ML501, simulations working again.
Path
/openrisc/trunk/orpsocv2/boards/README
/openrisc/trunk/orpsocv2/boards/readme.txt
/openrisc/trunk/orpsocv2/boards/xilinx/backend
/openrisc/trunk/orpsocv2/boards/xilinx/backend/rtl
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ddr2_model_parameters.vh
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/ddr2_model_parameters.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/ddr2_model_preload.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_phy_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/synthesis-defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/timescale.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/WireDelay.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/README
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/readme.txt
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_chipscope.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_ctrl.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_idelay_ctrl.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_infrastructure.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mem_if_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mig.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_calib.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_ctl_io.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dm_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dqs_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dq_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_init.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_io.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_write.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_addr_fifo.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_rd.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_wr.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/dummy_slave.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/eth_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_params.vh
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v.prev
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if_cache.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_gpio.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_mc.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_startup.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/reset_debounce.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ssram_controller.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/uart_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/usr_rst.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_bytebus.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_dbus.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_ibus.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/clkgen
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/clkgen/clkgen.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/gpio
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/gpio/gpio.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/dbg_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/i2c_master_slave_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-params.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/tap_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/uart_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/xilinx_ddr2_params.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/lfsr
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/lfsr/lfsr.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_chipscope.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_ctrl.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_idelay_ctrl.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_infrastructure.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_mem_if_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_mig.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_calib.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_ctl_io.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_dm_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_dqs_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_dq_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_init.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_io.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_phy_write.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_usr_addr_fifo.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_usr_rd.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_usr_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_usr_wr.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/README
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ssram
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ssram/xilinx_ssram.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_conbus_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_lfsr.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/modelsim.scr
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/out
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/bootrom
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/bootrom/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb.v
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_sc_sw.v
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.