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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [sim/] [bin/] - Rev 479

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  • Rev 479, 2011-01-17 05:44:06 GMT
  • Author: julius
  • Log message:
    ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting.

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