URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 67, 2010-02-16 08:58:52 GMT
• Author: julius

• Log message:

  New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory

Path
/openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v
/openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/boards
/openrisc/trunk/orpsocv2/boards/tools.inc
/openrisc/trunk/orpsocv2/boards/xilinx
/openrisc/trunk/orpsocv2/boards/xilinx/ml501
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ddr2_model_parameters.vh
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/par
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/ml501_xst.ucf
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_chipscope.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_ctrl.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_idelay_ctrl.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_infrastructure.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mem_if_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mig.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_calib.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_ctl_io.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dm_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dqs_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dq_iob.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_init.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_io.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_write.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_addr_fifo.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_rd.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_top.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_wr.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/dummy_slave.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/eth_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_params.vh
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v.prev
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if_cache.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_gpio.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_mc.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_startup.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/reset_debounce.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ssram_controller.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/uart_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/usr_rst.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_conbus_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_lfsr.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/modelsim.scr
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/run
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/run/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board.h
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot.ld
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot_reset.S
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio.ld
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio_reset.S
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.c
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.ld
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest_reset.S
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/Makefile
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501.xcf
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_ddr2_wb_if_cache.ngc
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_xst.tpl
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/timescale.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/post_norm.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_clgen.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_shift.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl
/openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_clgen.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_shift.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v
/openrisc/trunk/orpsocv2/sim/bin/icarus.scr
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sim/bin/modelsim.scr
/openrisc/trunk/orpsocv2/sim/bin/verilator.scr
/openrisc/trunk/orpsocv2/sw/support/reset.S
/openrisc/trunk/orpsocv2/sw/support/uart.c
/openrisc/trunk/orpsocv2/sw/support/uart.h
/openrisc/trunk/orpsocv2/sw/utils/bin2vmem.c