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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] - Rev 55

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Last modification

  • Rev 55, 2009-11-13 20:25:39 GMT
  • Author: julius
  • Log message:
    Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk
Path
/openrisc/trunk/orpsocv2/backend/gbuf.v
/openrisc/trunk/orpsocv2/backend/generic_buffers.v
/openrisc/trunk/orpsocv2/backend/generic_gbuf.v
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/copyright.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_buffers.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_gbuf.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_sync.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_txrx.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii/tmp.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_16_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v
/openrisc/trunk/orpsocv2/sim/bin/icarus.scr
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sim/bin/modelsim.scr
/openrisc/trunk/orpsocv2/sim/bin/verilator.scr

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