URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 426, 2010-11-17 00:50:30 GMT
• Author: julius

• Log message:

  ORPSoC update
  
  Reverted back to previous OR1200 instruction cache.
  (...which...)
  Fixed or1200-except test failure on generic model.
  
  ML501 build not passing or1200-except test. Tried disabling
  burst on the bus (memory server doesn't support it yet) to
  no avail. To be continued...

Path
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
/openrisc/trunk/orpsocv2/sw/tests/sdram/board
/openrisc/trunk/orpsocv2/sw/tests/sdram/board/Makefile
/openrisc/trunk/orpsocv2/sw/tests/sdram/board/sdram-rows.c
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-board-rows.c
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-cols.c
/openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-echo.c