OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] - Rev 462

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 462, 2011-01-07 06:51:10 GMT
  • Author: julius
  • Log message:
    ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

    RAM models updated.
Path
/openrisc/trunk/orpsocv2/bench/sysc/include/coff.h
/openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/elf.h
/openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h
/openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h
/openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h
/openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h
/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
/openrisc/trunk/orpsocv2/bench/sysc/include/ResetSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h
/openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h
/openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h
/openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/ResetSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v
/openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.