URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] - Rev 476

Rev 476, 2011-01-14 12:42:08 GMT
Author: julius
Log message:
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.

Path
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v
/openrisc/trunk/orpsocv2/sim/bin/Makefile