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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [orpsoc_top/] - Rev 360

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Last modification

  • Rev 360, 2010-09-10 17:51:01 GMT
  • Author: julius
  • Log message:
    First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken
Path
/openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v
/openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v
/openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v
/openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v
/openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v
/openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/cy7c1354.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_stim.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench_defines.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/WireDelay.v
/openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1200
/openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb
/openrisc/trunk/orpsocv2/rtl/verilog/components/smii
/openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl
/openrisc/trunk/orpsocv2/rtl/verilog/components/tap
/openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl
/openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines_old.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_register.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/dummy_slave.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth
/openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include
/openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/tap_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/uart_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap
/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v
/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1k_startup
/openrisc/trunk/orpsocv2/rtl/verilog/or1k_top
/openrisc/trunk/orpsocv2/rtl/verilog/or1200
/openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb
/openrisc/trunk/orpsocv2/rtl/verilog/smii
/openrisc/trunk/orpsocv2/rtl/verilog/spi_ctrl
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/raminfr.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart16550.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_debug_if.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_wb.v
/openrisc/trunk/orpsocv2/rtl/verilog/uart_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus
/openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3
/openrisc/trunk/orpsocv2/rtl/verilog/wb_sdram_ctrl
/openrisc/trunk/orpsocv2/rtl/verilog/wb_switch_b3
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sim/out
/openrisc/trunk/orpsocv2/sw/Makefile.inc

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