URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] - Rev 42

Rev 42, 2009-06-13 16:01:20 GMT
Author: julius
Log message:
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model

Path
/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
/openrisc/trunk/orpsocv2/sim/bin/Makefile