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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [spi/] [sim/] - Rev 403

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Last modification

  • Rev 403, 2010-11-01 19:26:38 GMT
  • Author: julius
  • Log message:
    ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.
Path
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
/openrisc/trunk/orpsocv2/bench/verilog/AT26DFxxx.v
/openrisc/trunk/orpsocv2/bench/verilog/include
/openrisc/trunk/orpsocv2/bench/verilog/include/orpsoc-testbench-defines.v
/openrisc/trunk/orpsocv2/bench/verilog/include/timescale.v
/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc-testbench-defines.v
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v
/openrisc/trunk/orpsocv2/bench/verilog/timescale.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_clockgen.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_crc.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_maccontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_macstatus.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_miim.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_outputcontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_random.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_receivecontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_register.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_registers.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxaddrcheck.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxstatem.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_shiftreg.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_spram_256x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_transmitcontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txstatem.v
/openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_wishbone.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
/openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_txrx.v
/openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus
/openrisc/trunk/orpsocv2/sim/bin/definesgen.inc
/openrisc/trunk/orpsocv2/sim/bin/icarus.scr
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sim/bin/modelsim.scr
/openrisc/trunk/orpsocv2/sim/bin/verilator.scr
/openrisc/trunk/orpsocv2/sw/board/include/board.h
/openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S
/openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave
/openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave
/openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c
/openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/include/i2c_master_slave.h
/openrisc/trunk/orpsocv2/sw/Makefile.inc
/openrisc/trunk/orpsocv2/sw/tests/eth/sim/Makefile
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c
/openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile
/openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c
/openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c

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