OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [uart/] [sim/] - Rev 393

Rev

Directory listing | View Log | RSS feed

Last modification

  • Rev 393, 2010-10-27 14:30:36 GMT
  • Author: julius
  • Log message:
    ORPSoCv2 software rearrangement in progress. Basic tests should now run again.
Path
/openrisc/trunk/orpsocv2/sim/bin/Makefile
/openrisc/trunk/orpsocv2/sw/apps
/openrisc/trunk/orpsocv2/sw/apps/dhry
/openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.h
/openrisc/trunk/orpsocv2/sw/apps/spiflash
/openrisc/trunk/orpsocv2/sw/apps/testfloat
/openrisc/trunk/orpsocv2/sw/board
/openrisc/trunk/orpsocv2/sw/board/include
/openrisc/trunk/orpsocv2/sw/board/include/board.h
/openrisc/trunk/orpsocv2/sw/bootrom/Makefile
/openrisc/trunk/orpsocv2/sw/dhry
/openrisc/trunk/orpsocv2/sw/drivers
/openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave
/openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/i2c_master_slave.c
/openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include
/openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include/i2c_master_slave.h
/openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/Makefile
/openrisc/trunk/orpsocv2/sw/drivers/or1200
/openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S
/openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c
/openrisc/trunk/orpsocv2/sw/drivers/or1200/include
/openrisc/trunk/orpsocv2/sw/drivers/or1200/include/int.h
/openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h
/openrisc/trunk/orpsocv2/sw/drivers/or1200/include/spr-defs.h
/openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c
/openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld
/openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-mmu.S
/openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c
/openrisc/trunk/orpsocv2/sw/drivers/simple-spi
/openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include
/openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include/simple-spi.h
/openrisc/trunk/orpsocv2/sw/drivers/simple-spi/Makefile
/openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c
/openrisc/trunk/orpsocv2/sw/drivers/uart
/openrisc/trunk/orpsocv2/sw/drivers/uart/include
/openrisc/trunk/orpsocv2/sw/drivers/uart/include/uart.h
/openrisc/trunk/orpsocv2/sw/drivers/uart/Makefile
/openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c
/openrisc/trunk/orpsocv2/sw/include/board.h
/openrisc/trunk/orpsocv2/sw/include/dhry.h
/openrisc/trunk/orpsocv2/sw/include/int.h
/openrisc/trunk/orpsocv2/sw/include/or32-utils.h
/openrisc/trunk/orpsocv2/sw/include/printf.h
/openrisc/trunk/orpsocv2/sw/include/simple-spi.h
/openrisc/trunk/orpsocv2/sw/include/spr-defs.h
/openrisc/trunk/orpsocv2/sw/include/uart.h
/openrisc/trunk/orpsocv2/sw/lib
/openrisc/trunk/orpsocv2/sw/lib/include
/openrisc/trunk/orpsocv2/sw/lib/include/cpu-utils.h
/openrisc/trunk/orpsocv2/sw/lib/include/lib-utils.h
/openrisc/trunk/orpsocv2/sw/lib/include/printf.h
/openrisc/trunk/orpsocv2/sw/lib/lib-utils.c
/openrisc/trunk/orpsocv2/sw/lib/Makefile
/openrisc/trunk/orpsocv2/sw/lib/printf.c
/openrisc/trunk/orpsocv2/sw/Makefile.inc
/openrisc/trunk/orpsocv2/sw/or1200/Makefile
/openrisc/trunk/orpsocv2/sw/or1200/or1200-cbasic.c
/openrisc/trunk/orpsocv2/sw/or1200/or1200-dctest.c
/openrisc/trunk/orpsocv2/sw/or1200/or1200-div.c
/openrisc/trunk/orpsocv2/sw/or1200/or1200-float.c
/openrisc/trunk/orpsocv2/sw/or1200/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/or1200/or1200-simple.c
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-basic.S
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-except.S
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-fp.S
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-linkregtest.S
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-mac.S
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-tick.S
/openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-ticksyscall.S
/openrisc/trunk/orpsocv2/sw/sdram/Makefile
/openrisc/trunk/orpsocv2/sw/sdram/sdram-bankrows.c
/openrisc/trunk/orpsocv2/sw/sdram/sdram-banks.c
/openrisc/trunk/orpsocv2/sw/sdram/sdram-board-rows.c
/openrisc/trunk/orpsocv2/sw/sdram/sdram-cols.c
/openrisc/trunk/orpsocv2/sw/sdram/sdram-rows.c
/openrisc/trunk/orpsocv2/sw/spi/Makefile
/openrisc/trunk/orpsocv2/sw/spi/spi-interrupt.c
/openrisc/trunk/orpsocv2/sw/spi/spi-simple.c
/openrisc/trunk/orpsocv2/sw/spiflash
/openrisc/trunk/orpsocv2/sw/support/crt0.S
/openrisc/trunk/orpsocv2/sw/support/exceptions.c
/openrisc/trunk/orpsocv2/sw/support/int.c
/openrisc/trunk/orpsocv2/sw/support/or32-utils.c
/openrisc/trunk/orpsocv2/sw/support/or32.ld
/openrisc/trunk/orpsocv2/sw/support/or1200-mmu.S
/openrisc/trunk/orpsocv2/sw/support/printf.c
/openrisc/trunk/orpsocv2/sw/support/simple-spi.c
/openrisc/trunk/orpsocv2/sw/support/uart.c
/openrisc/trunk/orpsocv2/sw/testfloat
/openrisc/trunk/orpsocv2/sw/tests
/openrisc/trunk/orpsocv2/sw/tests/or1200
/openrisc/trunk/orpsocv2/sw/tests/or1200/board
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/Makefile
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-div.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-simple.c
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-tick.S
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S
/openrisc/trunk/orpsocv2/sw/tests/sdram
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/Makefile
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-bankrows.c
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-banks.c
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-board-rows.c
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-cols.c
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c
/openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram.h
/openrisc/trunk/orpsocv2/sw/tests/spi
/openrisc/trunk/orpsocv2/sw/tests/spi/sim
/openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile
/openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c
/openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c
/openrisc/trunk/orpsocv2/sw/tests/uart
/openrisc/trunk/orpsocv2/sw/tests/uart/sim
/openrisc/trunk/orpsocv2/sw/tests/uart/sim/Makefile
/openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-echo.c
/openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c
/openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-simple.c
/openrisc/trunk/orpsocv2/sw/uart/Makefile
/openrisc/trunk/orpsocv2/sw/uart/uart-echo.c
/openrisc/trunk/orpsocv2/sw/uart/uart-interrupt.c
/openrisc/trunk/orpsocv2/sw/uart/uart-simple.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.