URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] - Rev 1022

Rev 1022, 2002-09-03 22:28:21 GMT
Author: lampret
Log message:
As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.

Path
/trunk/or1200/rtl/verilog/or1200_alu.v
/trunk/or1200/rtl/verilog/or1200_defines.v
/trunk/or1200/rtl/verilog/or1200_except.v
/trunk/or1200/rtl/verilog/or1200_mem2reg.v
/trunk/or1200/rtl/verilog/or1200_rfram_generic.v