URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [support/] - Rev 344

Rev 344, 2001-11-14 11:33:53 GMT
Author: markom
Log message:
added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model

Path
/trunk/gen_or1k_isa/sources/opcode/or32.c
/trunk/gen_or1k_isa/sources/or32.c
/trunk/insight/opcodes/or32.c
/trunk/or1ksim/cpu/common/parse.c
/trunk/or1ksim/cpu/common/stats.c
/trunk/or1ksim/cpu/or1k/except.c
/trunk/or1ksim/cpu/or16/execute.c
/trunk/or1ksim/cpu/or32/execute.c
/trunk/or1ksim/cpu/or32/or32.c
/trunk/or1ksim/mmu/dmmu.c
/trunk/or1ksim/mmu/immu.c
/trunk/or1ksim/peripheral/16450.c
/trunk/or1ksim/peripheral/16450.h
/trunk/or1ksim/peripheral/mc.c
/trunk/or1ksim/sim.cfg
/trunk/or1ksim/support/simprintf.c
/trunk/or1ksim/testbench/acv_uart.c
/trunk/or1ksim/testbench/acv_uart.cfg
/trunk/or1ksim/testbench/basic.s
/trunk/or1ksim/testbench/cfg.S
/trunk/or1ksim/testbench/except.ld
/trunk/or1ksim/testbench/except.S
/trunk/or1ksim/testbench/excpt.S
/trunk/or1ksim/testbench/Makefile.am
/trunk/or1ksim/testbench/Makefile.in
/trunk/or1ksim/toplevel.c