URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] - Rev 617

Rev 617, 2002-01-28 01:16:00 GMT
Author: lampret
Log message:
Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.

Path
/trunk/or1200/rtl/verilog/or1200_alu.v
/trunk/or1200/rtl/verilog/or1200_cpu.v
/trunk/or1200/rtl/verilog/or1200_ctrl.v
/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
/trunk/or1200/rtl/verilog/or1200_dc_top.v
/trunk/or1200/rtl/verilog/or1200_dmmu_tlb.v
/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
/trunk/or1200/rtl/verilog/or1200_du.v
/trunk/or1200/rtl/verilog/or1200_except.v
/trunk/or1200/rtl/verilog/or1200_freeze.v
/trunk/or1200/rtl/verilog/or1200_genpc.v
/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
/trunk/or1200/rtl/verilog/or1200_ic_top.v
/trunk/or1200/rtl/verilog/or1200_if.v
/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
/trunk/or1200/rtl/verilog/or1200_immu_top.v
/trunk/or1200/rtl/verilog/or1200_top.v
/trunk/or1200/rtl/verilog/or1200_tt.v