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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] - Rev 1327

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Last modification

  • Rev 1327, 2004-12-13 17:16:29 GMT
  • Author: jcastillo
  • Log message:
    Firt import of OR1200 over Celoxica RC203 platform
Path
/trunk/rc203soc
/trunk/rc203soc/backend
/trunk/rc203soc/backend/xilinx
/trunk/rc203soc/backend/xilinx/soc.ucf
/trunk/rc203soc/bench
/trunk/rc203soc/bench/models
/trunk/rc203soc/bench/models/zbtram.v
/trunk/rc203soc/bench/verilog
/trunk/rc203soc/bench/verilog/rc203_test.v
/trunk/rc203soc/rtl
/trunk/rc203soc/rtl/verilog
/trunk/rc203soc/rtl/verilog/dbg_interface
/trunk/rc203soc/rtl/verilog/dbg_interface/bench
/trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog
/trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/cpu_behavioral.v
/trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/dbg_tb.v
/trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/timescale.v
/trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/wb_model_defines.v
/trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/wb_slave_behavioral.v
/trunk/rc203soc/rtl/verilog/dbg_interface/doc
/trunk/rc203soc/rtl/verilog/dbg_interface/doc/DbgSupp.pdf
/trunk/rc203soc/rtl/verilog/dbg_interface/doc/DbgSupp_PB.pdf
/trunk/rc203soc/rtl/verilog/dbg_interface/doc/Debug Support Datasheet (prl.).pdf
/trunk/rc203soc/rtl/verilog/dbg_interface/doc/src
/trunk/rc203soc/rtl/verilog/dbg_interface/doc/src/DbgSupp.doc
/trunk/rc203soc/rtl/verilog/dbg_interface/doc/src/DbgSupp_PB.doc
/trunk/rc203soc/rtl/verilog/dbg_interface/doc/src/Debug Support Datasheet (prl.).doc
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/README.txt
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_defines.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_registers.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_crc32_d1.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_defines.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_register.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_top.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_wb.v
/trunk/rc203soc/rtl/verilog/dbg_interface/rtl/verilog/dbg_wb_defines.v
/trunk/rc203soc/rtl/verilog/dbg_interface/sim
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/bin
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/bin/cds.lib
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/bin/hdl.var
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/bin/INCA_libs
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/bin/INCA_libs/worklib
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/log
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/log/dir_keeper
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/out
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/out/dir_keeper
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/run
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/run/clean
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/run/run_sim
/trunk/rc203soc/rtl/verilog/dbg_interface/sim/rtl_sim/run/wave.do
/trunk/rc203soc/rtl/verilog/jtag
/trunk/rc203soc/rtl/verilog/jtag/cells
/trunk/rc203soc/rtl/verilog/jtag/cells/rtl
/trunk/rc203soc/rtl/verilog/jtag/cells/rtl/verilog
/trunk/rc203soc/rtl/verilog/jtag/cells/rtl/verilog/BiDirectionalCell.v
/trunk/rc203soc/rtl/verilog/jtag/cells/rtl/verilog/ControlCell.v
/trunk/rc203soc/rtl/verilog/jtag/cells/rtl/verilog/InputCell.v
/trunk/rc203soc/rtl/verilog/jtag/cells/rtl/verilog/OutputCell.v
/trunk/rc203soc/rtl/verilog/jtag/tap
/trunk/rc203soc/rtl/verilog/jtag/tap/doc
/trunk/rc203soc/rtl/verilog/jtag/tap/doc/jtag.pdf
/trunk/rc203soc/rtl/verilog/jtag/tap/doc/src
/trunk/rc203soc/rtl/verilog/jtag/tap/doc/src/jtag.doc
/trunk/rc203soc/rtl/verilog/jtag/tap/rtl
/trunk/rc203soc/rtl/verilog/jtag/tap/rtl/verilog
/trunk/rc203soc/rtl/verilog/jtag/tap/rtl/verilog/tap_defines.v
/trunk/rc203soc/rtl/verilog/jtag/tap/rtl/verilog/tap_top.v
/trunk/rc203soc/rtl/verilog/or1200
/trunk/rc203soc/rtl/verilog/or1200/bench
/trunk/rc203soc/rtl/verilog/or1200/bench/README
/trunk/rc203soc/rtl/verilog/or1200/doc
/trunk/rc203soc/rtl/verilog/or1200/doc/or1200_spec.doc
/trunk/rc203soc/rtl/verilog/or1200/doc/or1200_spec.pdf
/trunk/rc203soc/rtl/verilog/or1200/lib
/trunk/rc203soc/rtl/verilog/or1200/lib/README
/trunk/rc203soc/rtl/verilog/or1200/lint
/trunk/rc203soc/rtl/verilog/or1200/lint/bin
/trunk/rc203soc/rtl/verilog/or1200/lint/bin/README
/trunk/rc203soc/rtl/verilog/or1200/lint/bin/run_lint
/trunk/rc203soc/rtl/verilog/or1200/lint/log
/trunk/rc203soc/rtl/verilog/or1200/lint/log/README
/trunk/rc203soc/rtl/verilog/or1200/lint/run
/trunk/rc203soc/rtl/verilog/or1200/lint/run/README
/trunk/rc203soc/rtl/verilog/or1200/rtl
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_alu.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_du.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_except.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_if.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_pic.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_pm.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_rf.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_sb.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_top.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_tt.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
/trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/timescale.v
/trunk/rc203soc/rtl/verilog/or1200/sim
/trunk/rc203soc/rtl/verilog/or1200/sim/README
/trunk/rc203soc/rtl/verilog/or1200/syn
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/README
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/read_design.inc
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/run_syn
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/top.scr
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/log
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/log/README
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/out
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/out/README
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/run
/trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/run/README
/trunk/rc203soc/rtl/verilog/rc203
/trunk/rc203soc/rtl/verilog/rc203/rc203_romcontroller.v
/trunk/rc203soc/rtl/verilog/rc203/rc203_zbtcontroller.v
/trunk/rc203soc/rtl/verilog/soc.v
/trunk/rc203soc/rtl/verilog/tc_top.v
/trunk/rc203soc/rtl/verilog/uart16550
/trunk/rc203soc/rtl/verilog/uart16550/bench
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/readme.txt
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/test_cases
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/test_cases/uart_int.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_device.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_device_utilities.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_log.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_test.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_testbench.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_testbench_defines.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_testbench_utilities.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_wb_utilities.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/vapi.log
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/wb_mast.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/wb_master_model.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/wb_model_defines.v
/trunk/rc203soc/rtl/verilog/uart16550/bench/vhdl
/trunk/rc203soc/rtl/verilog/uart16550/bench/vhdl/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/Doc
/trunk/rc203soc/rtl/verilog/uart16550/Doc/src
/trunk/rc203soc/rtl/verilog/uart16550/Doc/src/UART_spec.doc
/trunk/rc203soc/rtl/verilog/uart16550/fv
/trunk/rc203soc/rtl/verilog/uart16550/fv/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/lint
/trunk/rc203soc/rtl/verilog/uart16550/lint/bin
/trunk/rc203soc/rtl/verilog/uart16550/lint/bin/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/lint/log
/trunk/rc203soc/rtl/verilog/uart16550/lint/log/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/lint/out
/trunk/rc203soc/rtl/verilog/uart16550/lint/out/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/lint/run
/trunk/rc203soc/rtl/verilog/uart16550/lint/run/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/rtl
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/timescale.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_defines.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_fifo.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_receiver.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_regs.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_top.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_transmitter.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_wb.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/raminfr.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/timescale.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_defines.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_regs.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_top.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_wb.v
/trunk/rc203soc/rtl/verilog/uart16550/rtl/vhdl
/trunk/rc203soc/rtl/verilog/uart16550/rtl/vhdl/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/bin
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/bin/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/log
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/log/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/out
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/out/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/run
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/run/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/src
/trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/src/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/bin
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/bin/nc.scr
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/bin/sim.tcl
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log/uart_interrupts_report.log
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/out
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/out/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run/run_signalscan
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run/run_sim
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run/run_sim.scr
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/src
/trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/src/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/syn
/trunk/rc203soc/rtl/verilog/uart16550/syn/bin
/trunk/rc203soc/rtl/verilog/uart16550/syn/bin/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/syn/log
/trunk/rc203soc/rtl/verilog/uart16550/syn/log/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/syn/out
/trunk/rc203soc/rtl/verilog/uart16550/syn/out/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/syn/run
/trunk/rc203soc/rtl/verilog/uart16550/syn/run/.keepme
/trunk/rc203soc/rtl/verilog/uart16550/syn/src
/trunk/rc203soc/rtl/verilog/uart16550/syn/src/.keepme
/trunk/rc203soc/syn
/trunk/rc203soc/syn/RAMB4_S4.v
/trunk/rc203soc/syn/RAMB4_S16.v
/trunk/rc203soc/syn/RAMB4_S16_S16.v

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