URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 108

Rev 108, 2003-08-08 16:36:33 GMT
Author: tadejm
Log message:
Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.

Path
/trunk/rtl/verilog/pci_bridge32.v
/trunk/rtl/verilog/pci_pciw_fifo_control.v
/trunk/rtl/verilog/pci_pciw_pcir_fifos.v
/trunk/rtl/verilog/pci_target32_interface.v
/trunk/rtl/verilog/pci_target32_sm.v
/trunk/rtl/verilog/pci_target_unit.v