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[/] [pci/] [tags/] [rel_9/] [rtl/] [verilog/] - Rev 108
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Last modification
- Rev 108, 2003-08-08 16:36:33 GMT
- Author: tadejm
- Log message:
- Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.