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[/] [pit/] [trunk/] [rtl/] [verilog/] - Rev 17

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Last modification

  • Rev 17, 2010-01-27 20:08:01 GMT
  • Author: rehayes
  • Log message:
    Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.

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