URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] [trunk/] [verif/] [tb/] - Rev 43

Rev 43, 2012-02-02 06:27:19 GMT
Author: dinesha
Log message:
Test bench automation to handle differ write/read burst sequence is supported now

Path
/sdr_ctrl/trunk/verif/log/core_sdr8_sim.log
/sdr_ctrl/trunk/verif/log/core_sdr16_sim.log
/sdr_ctrl/trunk/verif/log/core_sdr32_sim.log
/sdr_ctrl/trunk/verif/log/core_SDR_8BIT_basic_test1.log
/sdr_ctrl/trunk/verif/log/core_SDR_16BIT_basic_test1.log
/sdr_ctrl/trunk/verif/log/core_SDR_32BIT_basic_test1.log
/sdr_ctrl/trunk/verif/log/top_sdr8_sim.log
/sdr_ctrl/trunk/verif/log/top_sdr16_sim.log
/sdr_ctrl/trunk/verif/log/top_sdr32_sim.log
/sdr_ctrl/trunk/verif/log/top_SDR_8BIT_basic_test1.log
/sdr_ctrl/trunk/verif/log/top_SDR_16BIT_basic_test1.log
/sdr_ctrl/trunk/verif/log/top_SDR_32BIT_basic_test1.log
/sdr_ctrl/trunk/verif/run/run_modelsim
/sdr_ctrl/trunk/verif/tb/tb_core.sv
/sdr_ctrl/trunk/verif/tb/tb_top.sv