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https://opencores.org/ocsvn/single_port/single_port/trunk
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[/] [single_port/] [trunk/] [VHDL/] - Rev 14
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Last modification
- Rev 14, 2007-11-17 12:53:00 GMT
- Author: mgeng
- Log message:
- Address is only converted to integer when chip enable is active in order to avoid simulator warnings
