URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 88

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Last modification

Rev 88, 2011-04-07 18:29:56 GMT
Author: jt_eaton
Log message:
added xml files for test benches
added gEDA sym sch starter templates

Path
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/syn/Basys_mrisc_loop/Basys
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/syn/Basys_mrisc_loop/debug
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/Basys
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/debug
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/doc/geda
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/syn/Nexys2_soc_mrisc_io_mouse_mouse/debug
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/doc/geda
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/soc/design.soc
/socgen/trunk/projects/io/bin/repeater
/socgen/trunk/projects/logic/bin/repeater
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top.ext
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/dut
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/serial_rcvr/soc/design.soc
/socgen/trunk/projects/logic/ip/uart/soc/design.soc
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_display
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/svga_timing_generation
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/top
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/wave.sav
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/wave.sav
/socgen/trunk/projects/logic/ip/vga_char_ctrl/soc/design.soc
/socgen/trunk/projects/Mos6502/bin/repeater
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.ext_m
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.inst_2_test
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.io_irq_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.io_poll_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.irq_2_test
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.kim_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.tim_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_io_irq_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_io_poll_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_irq_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_kim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_tim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_2_test/dmp_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_2_test/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_2_test/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_irq_2/dmp_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_irq_2/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_irq_2/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_poll_2/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_poll_2/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/irq_2_test/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/irq_2_test/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/kim_2/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/kim_2/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/tim_2/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/tim_2/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/soc/design.soc
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/doc/geda
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/variants
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/tb.test_define.inst_2_test
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top.rtl
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/run/inst_2_test/test_define
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/soc/design.soc
/socgen/trunk/projects/pic_micro/bin/repeater
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.ind_mem
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.loop
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.rf1
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.rf2
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.rf3
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.sanity1
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.sanity2
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/top.ext
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/dut
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/ind_mem/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dut
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/loop/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dut
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dut
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dut
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dut
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dut
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.ind_mem
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.loop
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf1
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf2
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf3
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity1
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity2
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.io
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.out
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/ind_mem/dut
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/ind_mem/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/loop/dut
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/loop/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/rf1/dut
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/rf1/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/rf2/dut
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/rf2/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/rf3/dut
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/rf3/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/sanity1/dut
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/sanity1/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/sanity2/dut
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/run/sanity2/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/soc/sim/run/mouse_mrisc/dut
/socgen/trunk/projects/pic_micro/ip/soc/sim/run/mouse_mrisc/test_define
/socgen/trunk/projects/pic_micro/ip/soc/soc/design.soc
/socgen/trunk/projects/Testbench
/socgen/trunk/projects/Testbench/bin
/socgen/trunk/projects/Testbench/bin/repeater
/socgen/trunk/projects/Testbench/ip
/socgen/trunk/projects/Testbench/ip/clock_gen
/socgen/trunk/projects/Testbench/ip/clock_gen/bin
/socgen/trunk/projects/Testbench/ip/clock_gen/bin/Makefile
/socgen/trunk/projects/Testbench/ip/clock_gen/doc
/socgen/trunk/projects/Testbench/ip/clock_gen/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/clock_gen/doc/html
/socgen/trunk/projects/Testbench/ip/clock_gen/doc/png
/socgen/trunk/projects/Testbench/ip/clock_gen/doc/timing
/socgen/trunk/projects/Testbench/ip/clock_gen/rtl
/socgen/trunk/projects/Testbench/ip/clock_gen/rtl/verilog
/socgen/trunk/projects/Testbench/ip/clock_gen/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/clock_gen/rtl/xml
/socgen/trunk/projects/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml
/socgen/trunk/projects/Testbench/ip/clock_gen/soc
/socgen/trunk/projects/Testbench/ip/clock_gen/soc/design.soc
/socgen/trunk/projects/Testbench/ip/ps2_host
/socgen/trunk/projects/Testbench/ip/ps2_host/bin
/socgen/trunk/projects/Testbench/ip/ps2_host/bin/Makefile
/socgen/trunk/projects/Testbench/ip/ps2_host/doc
/socgen/trunk/projects/Testbench/ip/ps2_host/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/ps2_host/doc/html
/socgen/trunk/projects/Testbench/ip/ps2_host/doc/png
/socgen/trunk/projects/Testbench/ip/ps2_host/doc/timing
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/verilog
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/verilog/ps2h_probe
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/xml
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml
/socgen/trunk/projects/Testbench/ip/ps2_host/soc
/socgen/trunk/projects/Testbench/ip/ps2_host/soc/design.soc
/socgen/trunk/projects/Testbench/ip/ps2_model
/socgen/trunk/projects/Testbench/ip/ps2_model/bin
/socgen/trunk/projects/Testbench/ip/ps2_model/bin/Makefile
/socgen/trunk/projects/Testbench/ip/ps2_model/doc
/socgen/trunk/projects/Testbench/ip/ps2_model/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/ps2_model/doc/html
/socgen/trunk/projects/Testbench/ip/ps2_model/doc/png
/socgen/trunk/projects/Testbench/ip/ps2_model/doc/timing
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/verilog
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/verilog/ps2_probe
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/xml
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml
/socgen/trunk/projects/Testbench/ip/ps2_model/soc
/socgen/trunk/projects/Testbench/ip/ps2_model/soc/design.soc
/socgen/trunk/projects/Testbench/ip/uart_host
/socgen/trunk/projects/Testbench/ip/uart_host/bin
/socgen/trunk/projects/Testbench/ip/uart_host/bin/Makefile
/socgen/trunk/projects/Testbench/ip/uart_host/doc
/socgen/trunk/projects/Testbench/ip/uart_host/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/uart_host/doc/html
/socgen/trunk/projects/Testbench/ip/uart_host/doc/png
/socgen/trunk/projects/Testbench/ip/uart_host/doc/timing
/socgen/trunk/projects/Testbench/ip/uart_host/rtl
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/verilog
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/verilog/uarth_probe
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/xml
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/xml/uart_host.xml
/socgen/trunk/projects/Testbench/ip/uart_host/soc
/socgen/trunk/projects/Testbench/ip/uart_host/soc/design.soc
/socgen/trunk/projects/Testbench/ip/uart_model
/socgen/trunk/projects/Testbench/ip/uart_model/bin
/socgen/trunk/projects/Testbench/ip/uart_model/bin/Makefile
/socgen/trunk/projects/Testbench/ip/uart_model/doc
/socgen/trunk/projects/Testbench/ip/uart_model/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/uart_model/doc/html
/socgen/trunk/projects/Testbench/ip/uart_model/doc/png
/socgen/trunk/projects/Testbench/ip/uart_model/doc/timing
/socgen/trunk/projects/Testbench/ip/uart_model/rtl
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/verilog
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/verilog/divider
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/verilog/io_probe
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_rcvr
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_xmit
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/xml
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/xml/uart_model.xml
/socgen/trunk/projects/Testbench/ip/uart_model/soc
/socgen/trunk/projects/Testbench/ip/uart_model/soc/design.soc
/socgen/trunk/projects/Testbench/soc
/socgen/trunk/projects/Testbench/soc/library.soc
/socgen/trunk/projects/Testbench/sw
/socgen/trunk/tools/bin/build_filelists
/socgen/trunk/tools/bin/build_geda
/socgen/trunk/tools/bin/build_verilog
/socgen/trunk/tools/bin/Makefile.root
/socgen/trunk/tools/bin/soc_builder
/socgen/trunk/tools/bin/soc_link
/socgen/trunk/tools/bin/soc_link_1
/socgen/trunk/tools/bin/soc_link_2
/socgen/trunk/tools/etc
/socgen/trunk/tools/install/msp430-gcc-4.4.3
/socgen/trunk/tools/Jtag_programmers/etc/udev/rules.d/xusbdfwu.rules

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[/] [socgen/] - Rev 88

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