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[/] [socgen/] [trunk/] - Rev 117

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Last modification

Rev 117, 2012-07-16 22:12:35 GMT
Author: jt_eaton
Log message:
added yellow pages tools

Path
/socgen/trunk/Makefile
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/jtag/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/or1k/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/ip-xact
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/ip-xact
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml/cde_jtag_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_asic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_asic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_64_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_def.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_def.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/xml/Basys_mrisc_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_def.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_default.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_uart.xml
/socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/xml/Nexys2_minsoc_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/xml/io_ext_mem_interface_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/xml/io_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_gpio_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/xml/io_pic_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_mouse_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/xml/io_ps2_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/xml/io_timer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rxtx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_rx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/xml/io_uart_tx_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/xml/io_utimer_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/xml/io_vga_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic_def.xml
/socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/xml/io_vic_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/rtl/xml/disp_io_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/disp_io/sim/xml/disp_io_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/sim/xml/flash_memcontrl_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_byte.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp5.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp6.xml
/socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp9.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/rtl/xml/ps2_interface_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_mouse_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/sim/xml/ps2_interface_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_fifo_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/sim/xml/serial_rcvr_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rx.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rxtx.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_tx.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rxtx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_rx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/uart/sim/xml/uart_tx_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/rtl/xml/usb_epp_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/usb_epp/sim/xml/usb_epp_tb.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_def.xml
/socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/sim/xml/T6502_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu_def.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_tb.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic_def.xml
/socgen/trunk/projects/opencores.org/Mos6502/ip/T6502_cpu_alu_logic/sim/xml/T6502_cpu_alu_logic_tb.xml
/socgen/trunk/projects/opencores.org/or1k/bin/compile
/socgen/trunk/projects/opencores.org/or1k/bin/Makefile.or32
/socgen/trunk/projects/opencores.org/or1k/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/or1k/doc/src/journal.html
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_clkgen.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/xml/or1200_dbg_tb.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_alu.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_boot.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_cfgr.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_ctrl.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_du.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_except.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_freeze.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_genpc.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_if.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_lsu.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_operandmuxes.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_rf.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_sprs.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_spr_mux.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_wbmux.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/xml/or1200_fpu_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/defines.asic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/verilog/or1200_amultp2_32x32.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_asic.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_def.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/clkgen/rtl/xml/clkgen_def.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/dbg_if/rtl/xml/dbg_if_wb_cpu.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/orp_soc/ip/generic_orpsocv2/rtl/xml/generic_orpsocv2_ra_ti_ua.xml
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/socgen/trunk/projects/opencores.org/orp_soc/ip/jtag/ip-xact/design.xml
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/socgen/trunk/tools/yp/lib.pm

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