OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 90

Rev

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 90, 2011-04-29 02:58:56 GMT
  • Author: jt_eaton
  • Log message:
    now build all testbenches from ip-xact files and list as testbench in design.soc
Path
/socgen/trunk/Makefile
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/soc/design.soc
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/xml
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/soc/design.soc
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/xml
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/soc/design.soc
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/soc/design.soc
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
/socgen/trunk/projects/io/ip/io_ext_mem_interface/sim/xml
/socgen/trunk/projects/io/ip/io_ext_mem_interface/soc/design.soc
/socgen/trunk/projects/io/ip/io_gpio/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_gpio/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_gpio/rtl/xml/io_gpio.xml
/socgen/trunk/projects/io/ip/io_gpio/sim/xml
/socgen/trunk/projects/io/ip/io_gpio/soc/design.soc
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/tb.test_define.mouse_mouse
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/top.ext
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/top.ext.mouse
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_default.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_gpio.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_mouse_mouse.xml
/socgen/trunk/projects/io/ip/io_module/sim/run/default/dut
/socgen/trunk/projects/io/ip/io_module/sim/run/default/test_define
/socgen/trunk/projects/io/ip/io_module/sim/run/mouse/dut
/socgen/trunk/projects/io/ip/io_module/sim/run/mouse/test_define
/socgen/trunk/projects/io/ip/io_module/sim/verilog
/socgen/trunk/projects/io/ip/io_module/sim/verilog/tb.test_define.default
/socgen/trunk/projects/io/ip/io_module/sim/verilog/tb.test_define.mouse_mouse
/socgen/trunk/projects/io/ip/io_module/sim/verilog/top.ext
/socgen/trunk/projects/io/ip/io_module/sim/verilog/top.ext.mouse
/socgen/trunk/projects/io/ip/io_module/sim/xml
/socgen/trunk/projects/io/ip/io_module/sim/xml/io_module_default.xml
/socgen/trunk/projects/io/ip/io_module/sim/xml/io_module_mouse_mouse.xml
/socgen/trunk/projects/io/ip/io_module/soc/design.soc
/socgen/trunk/projects/io/ip/io_pic/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_pic/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_pic/rtl/xml/io_pic.xml
/socgen/trunk/projects/io/ip/io_pic/sim/xml
/socgen/trunk/projects/io/ip/io_pic/soc/design.soc
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/top.ext
/socgen/trunk/projects/io/ip/io_ps2/rtl/xml/io_ps2.xml
/socgen/trunk/projects/io/ip/io_ps2/rtl/xml/io_ps2_default.xml
/socgen/trunk/projects/io/ip/io_ps2/sim/run/default/dut
/socgen/trunk/projects/io/ip/io_ps2/sim/run/default/test_define
/socgen/trunk/projects/io/ip/io_ps2/sim/verilog
/socgen/trunk/projects/io/ip/io_ps2/sim/verilog/tb.test_define.default
/socgen/trunk/projects/io/ip/io_ps2/sim/verilog/top.ext
/socgen/trunk/projects/io/ip/io_ps2/sim/xml
/socgen/trunk/projects/io/ip/io_ps2/sim/xml/io_ps2_default.xml
/socgen/trunk/projects/io/ip/io_ps2/soc/design.soc
/socgen/trunk/projects/io/ip/io_timer/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_timer/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_timer/rtl/xml/io_timer.xml
/socgen/trunk/projects/io/ip/io_timer/sim/xml
/socgen/trunk/projects/io/ip/io_timer/soc/design.soc
/socgen/trunk/projects/io/ip/io_uart/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_uart/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_uart/rtl/xml/io_uart.xml
/socgen/trunk/projects/io/ip/io_uart/sim/xml
/socgen/trunk/projects/io/ip/io_uart/soc/design.soc
/socgen/trunk/projects/io/ip/io_utimer/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_utimer/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_utimer/rtl/xml/io_utimer.xml
/socgen/trunk/projects/io/ip/io_utimer/sim/xml
/socgen/trunk/projects/io/ip/io_utimer/soc/design.soc
/socgen/trunk/projects/io/ip/io_vga/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_vga/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_vga/rtl/xml/io_vga.xml
/socgen/trunk/projects/io/ip/io_vga/sim/xml
/socgen/trunk/projects/io/ip/io_vga/soc/design.soc
/socgen/trunk/projects/io/ip/io_vic/rtl/verilog/top
/socgen/trunk/projects/io/ip/io_vic/rtl/verilog/top.body
/socgen/trunk/projects/io/ip/io_vic/rtl/xml/io_vic.xml
/socgen/trunk/projects/io/ip/io_vic/sim/xml
/socgen/trunk/projects/io/ip/io_vic/soc/design.soc
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/top
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/disp_io/rtl/xml/disp_io.xml
/socgen/trunk/projects/logic/ip/disp_io/rtl/xml/disp_io_default.xml
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/dut
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/disp_io/sim/verilog
/socgen/trunk/projects/logic/ip/disp_io/sim/verilog/tb.ext
/socgen/trunk/projects/logic/ip/disp_io/sim/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/disp_io/sim/xml
/socgen/trunk/projects/logic/ip/disp_io/sim/xml/disp_io_default.xml
/socgen/trunk/projects/logic/ip/disp_io/soc/design.soc
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/top
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl_default.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/run/default/dut
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/verilog
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/verilog/tb.ext
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/xml/flash_memcontrl_default.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/soc/design.soc
/socgen/trunk/projects/logic/ip/micro_bus/doc/geda
/socgen/trunk/projects/logic/ip/micro_bus/rtl/verilog/top
/socgen/trunk/projects/logic/ip/micro_bus/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/micro_bus/rtl/xml/micro_bus.xml
/socgen/trunk/projects/logic/ip/micro_bus/sim/xml
/socgen/trunk/projects/logic/ip/micro_bus/soc/design.soc
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/tb.test_define.mouse
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/top
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/top.sim
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface_default.xml
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface_mouse.xml
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/dut
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/dut
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/test_define
/socgen/trunk/projects/logic/ip/ps2_interface/sim/verilog
/socgen/trunk/projects/logic/ip/ps2_interface/sim/verilog/tb.ext
/socgen/trunk/projects/logic/ip/ps2_interface/sim/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/ps2_interface/sim/verilog/tb.test_define.mouse
/socgen/trunk/projects/logic/ip/ps2_interface/sim/xml
/socgen/trunk/projects/logic/ip/ps2_interface/sim/xml/ps2_interface_default.xml
/socgen/trunk/projects/logic/ip/ps2_interface/sim/xml/ps2_interface_mouse.xml
/socgen/trunk/projects/logic/ip/ps2_interface/soc/design.soc
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/tb.test_define.fifo_default
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top.body.fifo
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/fifo_default
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/fifo_default/dmp_define
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/fifo_default/dut
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/fifo_default/test_define
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/fifo_default/wave.sav
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/verilog
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/verilog/tb.test_define.fifo_default
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/verilog/top.ext
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/xml
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/xml/serial_rcvr_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/xml/serial_rcvr_fifo_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/soc/design.soc
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.divide
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.rxtx_default
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.rx_default
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.body.rx
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.body.rxtx
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.body.tx
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.sim
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_default.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_divide.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rx.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rxtx.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rxtx_default.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rx_default.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_tx.xml
/socgen/trunk/projects/logic/ip/uart/sim/run/default/dut
/socgen/trunk/projects/logic/ip/uart/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/dut
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/test_define
/socgen/trunk/projects/logic/ip/uart/sim/run/rxtx_default
/socgen/trunk/projects/logic/ip/uart/sim/run/rxtx_default/dmp_define
/socgen/trunk/projects/logic/ip/uart/sim/run/rxtx_default/dut
/socgen/trunk/projects/logic/ip/uart/sim/run/rxtx_default/test_define
/socgen/trunk/projects/logic/ip/uart/sim/run/rxtx_default/wave.sav
/socgen/trunk/projects/logic/ip/uart/sim/run/rx_default
/socgen/trunk/projects/logic/ip/uart/sim/run/rx_default/dmp_define
/socgen/trunk/projects/logic/ip/uart/sim/run/rx_default/dut
/socgen/trunk/projects/logic/ip/uart/sim/run/rx_default/test_define
/socgen/trunk/projects/logic/ip/uart/sim/run/rx_default/wave.sav
/socgen/trunk/projects/logic/ip/uart/sim/verilog
/socgen/trunk/projects/logic/ip/uart/sim/verilog/tb.ext
/socgen/trunk/projects/logic/ip/uart/sim/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/uart/sim/verilog/tb.test_define.divide
/socgen/trunk/projects/logic/ip/uart/sim/verilog/tb.test_define.rxtx_default
/socgen/trunk/projects/logic/ip/uart/sim/verilog/tb.test_define.rx_default
/socgen/trunk/projects/logic/ip/uart/sim/xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_default.xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_divide.xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_rxtx_default.xml
/socgen/trunk/projects/logic/ip/uart/sim/xml/uart_rx_default.xml
/socgen/trunk/projects/logic/ip/uart/soc/design.soc
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/top
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml
/socgen/trunk/projects/logic/ip/usb_epp/rtl/xml/usb_epp_default.xml
/socgen/trunk/projects/logic/ip/usb_epp/sim/verilog
/socgen/trunk/projects/logic/ip/usb_epp/sim/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/usb_epp/sim/xml
/socgen/trunk/projects/logic/ip/usb_epp/sim/xml/usb_epp_default.xml
/socgen/trunk/projects/logic/ip/usb_epp/soc/design.soc
/socgen/trunk/projects/logic/ip/vga_char_ctrl/doc/geda
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_display
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_gen
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/tb.test_define.default_600x432
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/top
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/top.body
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_default.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_default_600x432.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/dut
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dut
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/test_define
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/verilog
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/verilog/tb.ext
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/verilog/tb.test_define.default_600x432
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_default.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_default_600x432.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/soc/design.soc
/socgen/trunk/projects/Mos6502/ip/T6502/doc/geda
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_io_irq_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_io_poll_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_irq_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_kim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_tim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_2_test/wave.sav
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.ext_m
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.test_define.inst_2_test
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.test_define.io_irq_2
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.test_define.io_poll_2
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.test_define.irq_2_test
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.test_define.kim_2
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.test_define.tim_2
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_io_irq_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_io_poll_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_irq_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_kim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_tim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/soc/design.soc
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top.body
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top.sim
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/verilog
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/verilog/tb.test_define.inst_2_test
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/verilog/top.rtl
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/soc/design.soc
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/doc/geda
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/tb.ext
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/tb.test_define.alu_logic_test
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/top
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/top.body
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic_alu_logic_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/run/alu_logic_test/dut
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/run/alu_logic_test/test_define
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/verilog
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/verilog/tb.ext
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/verilog/tb.test_define.alu_logic_test
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/xml/T6502_cpu_alu_logic_alu_logic_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/tb.test_define.ind_mem
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/tb.test_define.loop
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/tb.test_define.rf1
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/tb.test_define.rf2
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/tb.test_define.rf3
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/tb.test_define.sanity1
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/tb.test_define.sanity2
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/verilog/top.ext
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/xml/mrisc_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.body
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.sim
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/tb.test_define.ind_mem
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/tb.test_define.loop
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/tb.test_define.rf1
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/tb.test_define.rf2
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/tb.test_define.rf3
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/tb.test_define.sanity1
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/tb.test_define.sanity2
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/top.io
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/verilog/top.out
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/soc/rtl/verilog/tb.test_define.mouse_mrisc
/socgen/trunk/projects/pic_micro/ip/soc/rtl/verilog/top.ext.mouse_mrisc
/socgen/trunk/projects/pic_micro/ip/soc/rtl/xml/soc_mrisc_io.xml
/socgen/trunk/projects/pic_micro/ip/soc/rtl/xml/soc_mrisc_io_mouse_mrisc.xml
/socgen/trunk/projects/pic_micro/ip/soc/sim/run/mouse_mrisc/dut
/socgen/trunk/projects/pic_micro/ip/soc/sim/run/mouse_mrisc/test_define
/socgen/trunk/projects/pic_micro/ip/soc/sim/verilog
/socgen/trunk/projects/pic_micro/ip/soc/sim/verilog/tb.test_define.mouse
/socgen/trunk/projects/pic_micro/ip/soc/sim/verilog/tb.test_define.mouse_mrisc
/socgen/trunk/projects/pic_micro/ip/soc/sim/verilog/top.ext.mouse
/socgen/trunk/projects/pic_micro/ip/soc/sim/verilog/top.ext.mouse_mrisc
/socgen/trunk/projects/pic_micro/ip/soc/sim/xml
/socgen/trunk/projects/pic_micro/ip/soc/sim/xml/soc_mrisc_io_mouse_mrisc.xml
/socgen/trunk/projects/pic_micro/ip/soc/sim/xml/soc_pic16c5x_io_mouse.xml
/socgen/trunk/projects/pic_micro/ip/soc/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/soc/syn/Basys_soc_mrisc_io_mouse
/socgen/trunk/projects/pic_micro/ip/soc/syn/Nexys2_soc_mrisc_io_mouse
/socgen/trunk/projects/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml
/socgen/trunk/projects/Testbench/ip/clock_gen/sim
/socgen/trunk/projects/Testbench/ip/clock_gen/sim/xml
/socgen/trunk/projects/Testbench/ip/clock_gen/soc/design.soc
/socgen/trunk/projects/Testbench/ip/io_probe
/socgen/trunk/projects/Testbench/ip/io_probe/bin
/socgen/trunk/projects/Testbench/ip/io_probe/bin/Makefile
/socgen/trunk/projects/Testbench/ip/io_probe/doc
/socgen/trunk/projects/Testbench/ip/io_probe/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/io_probe/doc/html
/socgen/trunk/projects/Testbench/ip/io_probe/doc/png
/socgen/trunk/projects/Testbench/ip/io_probe/doc/timing
/socgen/trunk/projects/Testbench/ip/io_probe/rtl
/socgen/trunk/projects/Testbench/ip/io_probe/rtl/verilog
/socgen/trunk/projects/Testbench/ip/io_probe/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/io_probe/rtl/xml
/socgen/trunk/projects/Testbench/ip/io_probe/rtl/xml/io_probe.xml
/socgen/trunk/projects/Testbench/ip/io_probe/sim
/socgen/trunk/projects/Testbench/ip/io_probe/sim/xml
/socgen/trunk/projects/Testbench/ip/io_probe/soc
/socgen/trunk/projects/Testbench/ip/io_probe/soc/design.soc
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/verilog/ps2h_probe
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml
/socgen/trunk/projects/Testbench/ip/ps2_host/sim
/socgen/trunk/projects/Testbench/ip/ps2_host/sim/xml
/socgen/trunk/projects/Testbench/ip/ps2_host/soc/design.soc
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/verilog/ps2_probe
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml
/socgen/trunk/projects/Testbench/ip/ps2_model/sim
/socgen/trunk/projects/Testbench/ip/ps2_model/sim/xml
/socgen/trunk/projects/Testbench/ip/ps2_model/soc/design.soc
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/verilog/uarth_probe
/socgen/trunk/projects/Testbench/ip/uart_host/rtl/xml/uart_host.xml
/socgen/trunk/projects/Testbench/ip/uart_host/sim
/socgen/trunk/projects/Testbench/ip/uart_host/sim/xml
/socgen/trunk/projects/Testbench/ip/uart_host/soc/design.soc
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/verilog/io_probe
/socgen/trunk/projects/Testbench/ip/uart_model/rtl/xml/uart_model.xml
/socgen/trunk/projects/Testbench/ip/uart_model/sim
/socgen/trunk/projects/Testbench/ip/uart_model/sim/xml
/socgen/trunk/projects/Testbench/ip/uart_model/soc/design.soc
/socgen/trunk/targets/Basys/Pad_Ring.v
/socgen/trunk/targets/Nexys2/Pad_Ring.v
/socgen/trunk/tools/bin/build_filelists
/socgen/trunk/tools/bin/build_geda
/socgen/trunk/tools/bin/build_leaf
/socgen/trunk/tools/bin/build_verilog
/socgen/trunk/tools/bin/setup_cov
/socgen/trunk/tools/bin/soc_builder
/socgen/trunk/tools/bin/soc_generate
/socgen/trunk/tools/bin/soc_link
/socgen/trunk/tools/bin/soc_link_1
/socgen/trunk/tools/bin/soc_link_2
/socgen/trunk/tools/sys
/socgen/trunk/tools/sys/build_coverage
/socgen/trunk/tools/sys/build_fizzim
/socgen/trunk/tools/sys/build_geda
/socgen/trunk/tools/sys/build_leaf
/socgen/trunk/tools/sys/build_sim_filelists
/socgen/trunk/tools/sys/build_syn_filelists
/socgen/trunk/tools/sys/build_verilog
/socgen/trunk/tools/sys/soc_builder
/socgen/trunk/tools/sys/soc_generate
/socgen/trunk/tools/sys/soc_link
/socgen/trunk/tools/sys/soc_link_1
/socgen/trunk/tools/sys/soc_link_2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.