URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 92

Directory listing | View Log | Compare with Previous | RSS feed

Last modification

Rev 92, 2011-05-07 13:38:55 GMT
Author: jt_eaton
Log message:
all testbenchs now built from /sim/xml files
bench /models now in Testbench

Path
/socgen/trunk/bench/verilog/models
/socgen/trunk/bench/verilog/TestBench
/socgen/trunk/lib/cde_clock_sys/cde_clock_sys.v
/socgen/trunk/lib/cde_jtag/cde_jtag.v
/socgen/trunk/lib/doc/drawing/sch/cde_asyncdisable.sch
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/run/mrisc_loop/test_define
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/verilog
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/verilog/tb.test_define.loop
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/xml/Basys_mrisc_loop_sim.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/soc/design.soc
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/run/soc_mrisc_io_mouse_mrisc/dut
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/run/soc_mrisc_io_mouse_mrisc/test_define
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/verilog
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/verilog/tb.ext
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/verilog/tb.test_define.mouse
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_mouse_sim.xml
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/soc/design.soc
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/run/soc_mrisc_io_mouse_mouse_mrisc/dut
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/run/soc_mrisc_io_mouse_mouse_mrisc/test_define
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/verilog
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/verilog/tb.ext
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/verilog/tb.test_define.io_mouse_mouse
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_mouse_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/soc/design.soc
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_io_irq_2/dut
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_io_irq_2/test_define
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_io_poll_2/dut
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_io_poll_2/test_define
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_io_poll_2/wave.sav
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_irq_2_test/dut
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_irq_2_test/test_define
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_kim_2/dut
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_kim_2/test_define
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_tim_2/dut
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/run/T6502_tim_2/test_define
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog/tb.ext
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog/tb.test_define.io_irq_2
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog/tb.test_define.io_poll_2
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog/tb.test_define.irq_2_test
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog/tb.test_define.kim_2
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/verilog/tb.test_define.tim_2
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_io_irq_2_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_io_poll_2_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_irq_2_test_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_kim_2_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tim_2_sim.xml
/socgen/trunk/projects/fpgas/ip/Nexys2_T6502/soc/design.soc
/socgen/trunk/projects/io/ip/io_ext_mem_interface/soc/design.soc
/socgen/trunk/projects/io/ip/io_gpio/soc/design.soc
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/io/ip/io_module/rtl/verilog/tb.test_define.mouse_mouse
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_default.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_mouse_mouse.xml
/socgen/trunk/projects/io/ip/io_pic/soc/design.soc
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/io/ip/io_ps2/rtl/xml/io_ps2_default.xml
/socgen/trunk/projects/io/ip/io_timer/soc/design.soc
/socgen/trunk/projects/io/ip/io_uart/soc/design.soc
/socgen/trunk/projects/io/ip/io_utimer/soc/design.soc
/socgen/trunk/projects/io/ip/io_vga/soc/design.soc
/socgen/trunk/projects/io/ip/io_vic/soc/design.soc
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/disp_io/rtl/xml/disp_io_default.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl_default.xml
/socgen/trunk/projects/logic/ip/micro_bus/soc/design.soc
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/tb.test_define.mouse
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface_default.xml
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface_mouse.xml
/socgen/trunk/projects/logic/ip/ps2_interface/soc/design.soc
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/tb.test_define.fifo_default
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo_default.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/soc/design.soc
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.divide
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.rxtx_default
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/tb.test_define.rx_default
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_default.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_divide.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rxtx_default.xml
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart_rx_default.xml
/socgen/trunk/projects/logic/ip/uart/soc/design.soc
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/usb_epp/rtl/xml/usb_epp_default.xml
/socgen/trunk/projects/logic/ip/usb_epp/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/tb.ext
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/tb.test_define.default
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/tb.test_define.default_600x432
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_default.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_default_600x432.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.ext_m
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.inst_2_test
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.io_irq_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.io_poll_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.irq_2_test
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.kim_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/tb.test_define.tim_2
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_io_irq_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_io_poll_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_irq_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_kim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502_tim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/kim_2/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/verilog/tb.ext_m
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_io_irq_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_io_poll_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_irq_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_kim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/xml/T6502_tim_2.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/tb.test_define.inst_2_test
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_inst_2_test.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/tb.ext
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/tb.test_define.alu_logic_test
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic_alu_logic_test.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.ind_mem
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.loop
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.rf1
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.rf2
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.rf3
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.sanity1
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/tb.test_define.sanity2
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.ind_mem
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.loop
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf1
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf2
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf3
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity1
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity2
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_ind_mem.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_loop.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf3.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity1.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity2.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/soc/design.soc
/socgen/trunk/projects/pic_micro/ip/soc/rtl/verilog/tb.test_define.mouse_mrisc
/socgen/trunk/projects/pic_micro/ip/soc/rtl/xml/soc_mrisc_io_mouse_mrisc.xml
/socgen/trunk/projects/pic_micro/ip/soc/soc/design.soc
/socgen/trunk/projects/Testbench/ip/gpio_model
/socgen/trunk/projects/Testbench/ip/gpio_model/bin
/socgen/trunk/projects/Testbench/ip/gpio_model/bin/Makefile
/socgen/trunk/projects/Testbench/ip/gpio_model/doc
/socgen/trunk/projects/Testbench/ip/gpio_model/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/gpio_model/doc/html
/socgen/trunk/projects/Testbench/ip/gpio_model/doc/png
/socgen/trunk/projects/Testbench/ip/gpio_model/doc/timing
/socgen/trunk/projects/Testbench/ip/gpio_model/rtl
/socgen/trunk/projects/Testbench/ip/gpio_model/rtl/verilog
/socgen/trunk/projects/Testbench/ip/gpio_model/rtl/verilog/top
/socgen/trunk/projects/Testbench/ip/gpio_model/rtl/xml
/socgen/trunk/projects/Testbench/ip/gpio_model/rtl/xml/gpio_model.xml
/socgen/trunk/projects/Testbench/ip/gpio_model/sim
/socgen/trunk/projects/Testbench/ip/gpio_model/sim/xml
/socgen/trunk/projects/Testbench/ip/gpio_model/soc
/socgen/trunk/projects/Testbench/ip/gpio_model/soc/design.soc
/socgen/trunk/projects/Testbench/ip/template
/socgen/trunk/projects/Testbench/ip/template/bin
/socgen/trunk/projects/Testbench/ip/template/bin/Makefile
/socgen/trunk/projects/Testbench/ip/template/doc
/socgen/trunk/projects/Testbench/ip/template/doc/copyright.v
/socgen/trunk/projects/Testbench/ip/template/doc/html
/socgen/trunk/projects/Testbench/ip/template/doc/png
/socgen/trunk/projects/Testbench/ip/template/doc/timing
/socgen/trunk/projects/Testbench/ip/template/rtl
/socgen/trunk/projects/Testbench/ip/template/rtl/verilog
/socgen/trunk/projects/Testbench/ip/template/rtl/verilog/xxx
/socgen/trunk/projects/Testbench/ip/template/rtl/xml
/socgen/trunk/projects/Testbench/ip/template/rtl/xml/xxx.xml
/socgen/trunk/projects/Testbench/ip/template/sim
/socgen/trunk/projects/Testbench/ip/template/sim/xml
/socgen/trunk/projects/Testbench/ip/template/soc
/socgen/trunk/projects/Testbench/ip/template/soc/design.soc
/socgen/trunk/tools/fizzim
/socgen/trunk/tools/install/Ubuntu_9.04
/socgen/trunk/tools/or32
/socgen/trunk/tools/sys/build_sim_filelists
/socgen/trunk/tools/sys/build_verilog
/socgen/trunk/tools/sys/soc_builder
/socgen/trunk/tools/sys/soc_link
/socgen/trunk/tools/sys/soc_link_1
/socgen/trunk/tools/sys/soc_link_2

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 92

Last modification