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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] - Rev 134

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Last modification

  • Rev 134, 2015-06-10 17:23:02 GMT
  • Author: jt_eaton
  • Log message:
    Resynced database
    socgen now supports elaboration
    Bad news is that it is now alot slower.
Path
/socgen/trunk/common/opencores.org/cde/ip/clock/doc/Geda/html/cde_clock_sys.html
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/verilog/clock_gater
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/verilog/clock_sys
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/verilog/clock_sys.v
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/verilog/copyright
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/verilog/sim/dll
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/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/verilog/timescale
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/xml/cde_clock_dll.xml
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/xml/cde_clock_sys.design.xml
/socgen/trunk/common/opencores.org/cde/ip/clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/common/opencores.org/cde/ip/divider/rtl/verilog/copyright
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/socgen/trunk/common/opencores.org/cde/ip/fifo/componentCfg.xml
/socgen/trunk/common/opencores.org/cde/ip/fifo/doc/Geda/html/cde_fifo_def.html
/socgen/trunk/common/opencores.org/cde/ip/fifo/rtl/verilog/fifo_def
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