OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] - Rev 133

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Last modification

  • Rev 133, 2015-04-28 16:24:59 GMT
  • Author: jt_eaton
  • Log message:
    Added Desing databases and foundation for elaborations tools
Path
/socgen/trunk/common/opencores.org/Busdefs/or1k
/socgen/trunk/common/opencores.org/Busdefs/or1k/componentCfg.xml
/socgen/trunk/common/opencores.org/Busdefs/or1k/xml
/socgen/trunk/common/opencores.org/Busdefs/or1k/xml/or1k_cpu.busDefinition.xml
/socgen/trunk/common/opencores.org/Busdefs/or1k/xml/or1k_cpu_rtl.abstractionDefinition.xml
/socgen/trunk/common/opencores.org/Busdefs/or1k/xml/or1k_dbg.busDefinition.xml
/socgen/trunk/common/opencores.org/Busdefs/or1k/xml/or1k_dbg_rtl.abstractionDefinition.xml
/socgen/trunk/common/opencores.org/Busdefs/or1k/xml/or1k_spr.busDefinition.xml
/socgen/trunk/common/opencores.org/Busdefs/or1k/xml/or1k_spr_rtl.abstractionDefinition.xml
/socgen/trunk/common/opencores.org/cde/ip/fifo/doc/Geda/html/cde_fifo_def.html
/socgen/trunk/common/opencores.org/cde/ip/fifo/doc/Geda/src/cde_fifo_def.v
/socgen/trunk/common/opencores.org/cde/ip/fifo/rtl/verilog/fifo_def.v
/socgen/trunk/common/opencores.org/cde/ip/fifo/rtl/xml/cde_fifo_def.design.xml
/socgen/trunk/common/opencores.org/cde/ip/fifo/rtl/xml/cde_fifo_def.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_classic_sync.html
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_sync.html
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_tap.html
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/sch/cde_jtag_classic_sync.sch
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/sch/cde_jtag_tap.sch
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/src/cde_jtag_tap.v
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/sym/cde_jtag_classic_sync.sym
/socgen/trunk/common/opencores.org/cde/ip/jtag/doc/Geda/sym/cde_jtag_tap.sym
/socgen/trunk/common/opencores.org/cde/ip/jtag/rtl/verilog/jtag_tap
/socgen/trunk/common/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_classic_sync.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_sync.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/rtl/xml/cde_jtag_tap.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_bfm.design.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_classic_bfm.design.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_classic_sync_bfm.design.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/cde_jtag_tap_lint.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/jtag_classic_rpc_in_reg_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/jtag_classic_rpc_reg_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/jtag_rpc_in_reg_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/jtag_rpc_reg_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/jtag_tap_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/jtag/sim/testbenches/xml/jtag_tap_dutg.design.xml
/socgen/trunk/common/opencores.org/cde/ip/lifo/doc/Geda/html/cde_lifo_def.html
/socgen/trunk/common/opencores.org/cde/ip/lifo/rtl/xml/cde_lifo_def.design.xml
/socgen/trunk/common/opencores.org/cde/ip/lifo/rtl/xml/cde_lifo_def.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/componentCfg.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/doc/Geda/html/cde_mult_generic.html
/socgen/trunk/common/opencores.org/cde/ip/mult/doc/Geda/html/cde_mult_ord_r4.html
/socgen/trunk/common/opencores.org/cde/ip/mult/doc/Geda/html/cde_mult_serial.html
/socgen/trunk/common/opencores.org/cde/ip/mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/verilog/top
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_bfm.design.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_generic_lint.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_generic_tb.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_ord_r4_lint.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_serial_lint.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/cde_mult_serial_tb.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/mult_generic_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/mult_ord_r4_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/mult/sim/testbenches/xml/mult_serial_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/pad/doc/Geda/html/cde_pad_se0_dig.html
/socgen/trunk/common/opencores.org/cde/ip/pad/doc/Geda/sch/cde_pad_se0_dig.sch
/socgen/trunk/common/opencores.org/cde/ip/pad/doc/Geda/src/cde_pad_se0_dig.v
/socgen/trunk/common/opencores.org/cde/ip/pad/doc/Geda/sym/cde_pad_se0_dig.sym
/socgen/trunk/common/opencores.org/cde/ip/pad/doc/html/cde_pad_se0_dig.html
/socgen/trunk/common/opencores.org/cde/ip/pad/rtl/verilog/pad_se0_dig.v
/socgen/trunk/common/opencores.org/cde/ip/pad/rtl/xml/cde_pad_se0_dig.xml
/socgen/trunk/common/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_both_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_rcvr_lint.xml
/socgen/trunk/common/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_xmit_lint.xml
/socgen/trunk/common/opencores.org/cde/ip/serial/sim/testbenches/xml/serial_rcvr_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/serial/sim/testbenches/xml/serial_xmit_dut.params.xml
/socgen/trunk/common/opencores.org/cde/ip/sram/doc/Geda/html/cde_sram_byte.html
/socgen/trunk/common/opencores.org/cde/ip/sram/doc/Geda/sch/cde_sram_byte.sch
/socgen/trunk/common/opencores.org/cde/ip/sram/doc/Geda/src/cde_sram_byte.v
/socgen/trunk/common/opencores.org/cde/ip/sram/doc/Geda/sym/cde_sram_byte.sym
/socgen/trunk/common/opencores.org/cde/ip/sram/doc/html/cde_sram_byte.html
/socgen/trunk/common/opencores.org/cde/ip/sram/rtl/verilog/lint/sram_byte.v
/socgen/trunk/common/opencores.org/cde/ip/sram/rtl/verilog/sram_byte.v
/socgen/trunk/common/opencores.org/cde/ip/sram/rtl/xml/sram_byte.xml
/socgen/trunk/common/opencores.org/cde/ip/sram/rtl/xml/sram_word.design.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/clock_gen/rtl/xml/clock_gen_def.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model/componentCfg.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model/rtl
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model/rtl/verilog
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model/rtl/verilog/copyright.v
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model/rtl/verilog/top.rtl
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model/rtl/xml
/socgen/trunk/common/opencores.org/Testbench/bfms/display_model/rtl/xml/display_model_def.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/io_probe/rtl/xml/io_probe_def.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/io_probe/rtl/xml/io_probe_in.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/micro_bus_model/rtl/verilog/top.sim
/socgen/trunk/common/opencores.org/Testbench/bfms/micro_bus_model/rtl/verilog/top.syn
/socgen/trunk/common/opencores.org/Testbench/bfms/micro_bus_model/rtl/xml/micro_bus_model_def.design.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/micro_bus_model/rtl/xml/micro_bus_model_def.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.sim
/socgen/trunk/common/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.syn
/socgen/trunk/common/opencores.org/Testbench/bfms/ps2_model/rtl/verilog/top.rtl
/socgen/trunk/common/opencores.org/Testbench/bfms/ps2_model/rtl/xml/ps2_model_def.design.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/ps2_model/rtl/xml/ps2_model_def.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/uart_model/rtl/verilog/top.rtl
/socgen/trunk/common/opencores.org/Testbench/bfms/uart_model/rtl/xml/uart_model_def.design.xml
/socgen/trunk/common/opencores.org/Testbench/bfms/uart_model/rtl/xml/uart_model_def.xml
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/html/display_model_def.html
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/html/micro_bus_model_def.html
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/html/ps2_model_def.html
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/html/uart_model_def.html
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/sch/display_model_def.sch
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/sch/micro_bus_model_def.sch
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/display_model_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/io_probe_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/io_probe_in.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/micro_bus_model_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/mt45w8mw12_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/or1200_dbg_model_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/ps2_model_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/uart_model_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/src/vga_model_def.v
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/sym/display_model_def.sym
/socgen/trunk/common/opencores.org/Testbench/doc/Geda/sym/micro_bus_model_def.sym
/socgen/trunk/common/opencores.org/Testbench/doc/html/display_model_def.html
/socgen/trunk/common/opencores.org/Testbench/toolflows/toolflow/xml/ise.xml
/socgen/trunk/common/opencores.org/Testbench/toolflows/toolflow/xml/verilog.xml
/socgen/trunk/dbs
/socgen/trunk/Makefile
/socgen/trunk/Projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_core.xml
/socgen/trunk/Projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_design.xml
/socgen/trunk/Projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_design.xml
/socgen/trunk/Projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_padring.xml
/socgen/trunk/Projects/digilentinc.com/Nexys2/ip/jtag/rtl/verilog/syn/jtag_tap.v
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_cpu0.html
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_cpu1.html
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0.html
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0_jfifo.html
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0_jsp.html
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu2_jsp.html
/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_cpu0.sch
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