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[/] [socgen/] [trunk/] [doc/] [src/] - Rev 27

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Last modification

  • Rev 27, 2010-05-16 02:49:55 GMT
  • Author: jt_eaton
  • Log message:
    added uart and ps2 host and models
    added more documentation
Path
/socgen/trunk/bench/verilog/models/clock_gen.v
/socgen/trunk/bench/verilog/models/micro_bus_model.v
/socgen/trunk/bench/verilog/models/ps2_host.v
/socgen/trunk/bench/verilog/models/ps2_model.v
/socgen/trunk/bench/verilog/models/uart_host.v
/socgen/trunk/bench/verilog/models/uart_model.v
/socgen/trunk/bench/verilog/models/UART_Mon.v
/socgen/trunk/bench/verilog/TestBench
/socgen/trunk/doc/src/drawing/sch/reset_fig1.sch
/socgen/trunk/doc/src/drawing/sch/reset_fig2.sch
/socgen/trunk/doc/src/drawing/sch/supply_chain.sch
/socgen/trunk/doc/src/drawing/sch/ver_fig1.sch
/socgen/trunk/doc/src/drawing/sch/ver_fig2.sch
/socgen/trunk/doc/src/drawing/sch/ver_fig3.sch
/socgen/trunk/doc/src/guides/guide_database.html
/socgen/trunk/doc/src/guides/guide_documentation.html
/socgen/trunk/doc/src/guides/guide_verification.html
/socgen/trunk/doc/src/guides/reset_sys_design.html
/socgen/trunk/doc/src/png/reset_fig1.png
/socgen/trunk/doc/src/png/reset_fig2.png
/socgen/trunk/doc/src/png/supply_chain.png
/socgen/trunk/doc/src/png/ver_fig1.png
/socgen/trunk/doc/src/png/ver_fig2.png
/socgen/trunk/doc/src/png/ver_fig3.png
/socgen/trunk/doc/template/data_sheet.html
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/disp_io.v
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/dut
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/liblist
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/timescale.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_ps2.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_uart.v
/socgen/trunk/projects/logic/ip/io_module/sim/run/default/dut
/socgen/trunk/projects/logic/ip/io_module/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/dmp_define
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/dut
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/filelist
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/liblist
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/modellist
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/TB.defs
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/test_define
/socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/filelist
/socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/sch/cde_sync_with_hysteresis.sch
/socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/sch/ps2_interface.sch
/socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/sch/ps2_interface_fsm.sch
/socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/sym/cde_sync_with_hysteresis.sym
/socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/sym/ps2_interface.sym
/socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/sym/ps2_interface_fsm.sym
/socgen/trunk/projects/logic/ip/ps2_interface/doc/png/ps2_interface.png
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface.v
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/dut
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/modellist
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/dmp_define
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/dut
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/filelist
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/liblist
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/modellist
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/sav.sav
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/TB.defs
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/test_define
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/serial_xmit/bin/Makefile
/socgen/trunk/projects/logic/ip/serial_xmit/doc/copyright.v
/socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/filelist
/socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/sch/serial_xmit.sch
/socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/sym/serial_xmit.sym
/socgen/trunk/projects/logic/ip/serial_xmit/doc/html/serial_xmit.html
/socgen/trunk/projects/logic/ip/serial_xmit/doc/index.html
/socgen/trunk/projects/logic/ip/serial_xmit/doc/png/serial_xmit.png
/socgen/trunk/projects/logic/ip/serial_xmit/rtl/variants/serial_xmit/serial_xmit_defines.v
/socgen/trunk/projects/logic/ip/serial_xmit/rtl/verilog/serial_xmit.v
/socgen/trunk/projects/logic/ip/serial_xmit/sim/bin/Makefile
/socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/dmp_define
/socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/dut
/socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/filelist
/socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/liblist
/socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/modellist
/socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/TB.defs
/socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/uart/rtl/variants/uart_div
/socgen/trunk/projects/logic/ip/uart/rtl/variants/uart_div/uart_defines.v
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/uart.v
/socgen/trunk/projects/logic/ip/uart/sim/run/default/dut
/socgen/trunk/projects/logic/ip/uart/sim/run/default/modellist
/socgen/trunk/projects/logic/ip/uart/sim/run/default/TB.defs
/socgen/trunk/projects/logic/ip/uart/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/uart/sim/run/divide
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/dmp_define
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/dut
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/filelist
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/liblist
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/modellist
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/TB.defs
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/loop/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/loop/timescale.v
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/timescale.v
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/timescale.v
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/timescale.v
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/timescale.v
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/test_define
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/timescale.v
/socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist
/socgen/trunk/projects/pic_micro/ip/soc_mouse/rtl/verilog/soc_mouse.v
/socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/dut
/socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/test_define
/socgen/trunk/targets/Basys/Pad_Ring.v
/socgen/trunk/targets/Nexys2/Pad_Ring.v
/socgen/trunk/tools/geda/dot_gEDA/sym/regs/reg_pre.sym
/socgen/trunk/tools/geda/dot_gEDA/sym/regs/reg_rst.sym
/socgen/trunk/tools/geda/dot_gEDA/sym/regs/veg_pre.sym
/socgen/trunk/tools/install/Ubuntu_10.4/Makefile

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