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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] - Rev 39

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Last modification

  • Rev 39, 2010-06-29 05:26:55 GMT
  • Author: jt_eaton
  • Log message:
    added io_probe to sims
    added boot rom into 6502
    added T6502_control
Path
/socgen/trunk/bench/verilog/models/io_probe.v
/socgen/trunk/bench/verilog/models/io_probe_gates.v
/socgen/trunk/bench/verilog/models/micro_bus_model.v
/socgen/trunk/bench/verilog/models/ps2_host.v
/socgen/trunk/bench/verilog/models/ps2_model.v
/socgen/trunk/bench/verilog/models/timed_tester.v
/socgen/trunk/bench/verilog/models/uart_host.v
/socgen/trunk/bench/verilog/models/uart_model.v
/socgen/trunk/doc/src/drawing/sch/ver_fig1.sch
/socgen/trunk/doc/src/drawing/sch/ver_fig5.sch
/socgen/trunk/doc/src/drawing/sch/ver_fig6.sch
/socgen/trunk/doc/src/png/ver_fig1.png
/socgen/trunk/doc/src/png/ver_fig5.png
/socgen/trunk/doc/src/png/ver_fig6.png
/socgen/trunk/projects/logic/ip/disp_io/sim/run/default/modellist
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_pic.v
/socgen/trunk/projects/logic/ip/io_module/sim/run/default/modellist
/socgen/trunk/projects/logic/ip/io_module/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/modellist
/socgen/trunk/projects/logic/ip/io_module/sim/run/mouse/test_define
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/modellist
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/ps2_interface/sim/run/mouse/modellist
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/uart.v
/socgen/trunk/projects/logic/ip/uart/sim/run/default/modellist
/socgen/trunk/projects/logic/ip/uart/sim/run/default/test_define
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/modellist
/socgen/trunk/projects/logic/ip/uart/sim/run/divide/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/doc/T6502_doc.txt
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/variants/T6502/T6502_defines.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_alu.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_alu_ctrl.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_control.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_core.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_indexer.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_inst_decode.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_sequencer.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_state_fsm.v
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/modellist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/TB.defs
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/dmp_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/filelist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/liblist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/modellist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/TB.defs
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_test/wav.sav
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/modellist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/TB.defs
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_1_test/modellist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/modellist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/tim_1/dut
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/tim_1/modellist
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/tim_1/TB.defs
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/tim_1/test_define
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/core.v
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_io_poll/def_file
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_tim_1/core.v
/socgen/trunk/projects/Mos6502/ip/T6502/syn/Nexys2_T6502_tim_1/def_file
/socgen/trunk/projects/Mos6502/sw/boot
/socgen/trunk/projects/Mos6502/sw/boot/boot.asm
/socgen/trunk/projects/Mos6502/sw/boot/Makefile
/socgen/trunk/projects/Mos6502/sw/inst_test
/socgen/trunk/projects/Mos6502/sw/inst_test/inst_test.asm
/socgen/trunk/projects/Mos6502/sw/inst_test/Makefile
/socgen/trunk/projects/Mos6502/sw/io_irq
/socgen/trunk/projects/Mos6502/sw/io_irq/io_irq.asm
/socgen/trunk/projects/Mos6502/sw/io_irq/Makefile
/socgen/trunk/projects/Mos6502/sw/io_module
/socgen/trunk/projects/Mos6502/sw/io_module/io_module.asm
/socgen/trunk/projects/Mos6502/sw/io_module/Makefile
/socgen/trunk/projects/Mos6502/sw/io_poll/io_poll.asm
/socgen/trunk/projects/Mos6502/sw/irq_test
/socgen/trunk/projects/Mos6502/sw/irq_test/irq_test.asm
/socgen/trunk/projects/Mos6502/sw/irq_test/Makefile
/socgen/trunk/projects/Mos6502/sw/prog_test/prog_test.asm
/socgen/trunk/projects/Mos6502/sw/tim_1/tim_1.asm
/socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/modellist
/socgen/trunk/targets/Nexys2/lib/syn/cde_clock_sys/cde_clock_sys.v

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