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[/] [socgen/] [trunk/] [doc/] [src/] [drawing/] [sch/] - Rev 81

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Last modification

  • Rev 81, 2010-12-16 19:51:57 GMT
  • Author: jt_eaton
  • Log message:
    morphing xml files to use 1685
    removed log directories
Path
/socgen/trunk/bench/verilog/TestBench.ver
/socgen/trunk/doc/manifesto.pdf
/socgen/trunk/doc/prj_description.pdf
/socgen/trunk/doc/src/drawing/sch/data_fig2.sch
/socgen/trunk/doc/src/drawing/sch/data_fig3.sch
/socgen/trunk/doc/src/drawing/sch/data_fig5.sch
/socgen/trunk/doc/src/drawing/sch/naming_guide_1.png
/socgen/trunk/doc/src/guides/guide_database.html
/socgen/trunk/doc/src/png/data_fig2.png
/socgen/trunk/doc/src/png/data_fig3.png
/socgen/trunk/lib/doc/drawing/cde_asyncdisable.png
/socgen/trunk/lib/doc/drawing/sym/cde_prescale.sym
/socgen/trunk/lib/doc/html/cde_pads.html
/socgen/trunk/lib/doc/html/cde_prescale.html
/socgen/trunk/lib/doc/png/cde_prescale.png
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/variants
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
/socgen/trunk/projects/io/ip/io_ext_mem_interface/sim/log
/socgen/trunk/projects/io/ip/io_gpio/rtl/variants
/socgen/trunk/projects/io/ip/io_gpio/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_gpio/rtl/xml/io_gpio.xml
/socgen/trunk/projects/io/ip/io_gpio/sim/log
/socgen/trunk/projects/io/ip/io_module/rtl/variants
/socgen/trunk/projects/io/ip/io_module/rtl/verilog
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module.xml
/socgen/trunk/projects/io/ip/io_module/rtl/xml/io_module_mouse.xml
/socgen/trunk/projects/io/ip/io_module/sim/log
/socgen/trunk/projects/io/ip/io_pic/rtl/variants
/socgen/trunk/projects/io/ip/io_pic/rtl/verilog/micro_reg.v
/socgen/trunk/projects/io/ip/io_pic/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_pic/rtl/xml/io_pic.xml
/socgen/trunk/projects/io/ip/io_pic/sim/log
/socgen/trunk/projects/io/ip/io_ps2/rtl/variants
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/micro_reg.v
/socgen/trunk/projects/io/ip/io_ps2/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_ps2/rtl/xml/io_ps2.xml
/socgen/trunk/projects/io/ip/io_ps2/sim/log
/socgen/trunk/projects/io/ip/io_timer/rtl/variants
/socgen/trunk/projects/io/ip/io_timer/rtl/verilog/micro_reg.v
/socgen/trunk/projects/io/ip/io_timer/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_timer/rtl/xml/io_timer.xml
/socgen/trunk/projects/io/ip/io_timer/sim/log
/socgen/trunk/projects/io/ip/io_uart/rtl/variants
/socgen/trunk/projects/io/ip/io_uart/rtl/verilog/micro_reg.v
/socgen/trunk/projects/io/ip/io_uart/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_uart/rtl/xml/io_uart.xml
/socgen/trunk/projects/io/ip/io_uart/sim/log
/socgen/trunk/projects/io/ip/io_utimer/rtl/variants
/socgen/trunk/projects/io/ip/io_utimer/rtl/verilog/micro_reg.v
/socgen/trunk/projects/io/ip/io_utimer/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_utimer/rtl/xml/io_utimer.xml
/socgen/trunk/projects/io/ip/io_utimer/sim/log
/socgen/trunk/projects/io/ip/io_vga/rtl/variants
/socgen/trunk/projects/io/ip/io_vga/rtl/verilog/micro_reg.v
/socgen/trunk/projects/io/ip/io_vga/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_vga/rtl/xml/io_vga.xml
/socgen/trunk/projects/io/ip/io_vga/sim/log
/socgen/trunk/projects/io/ip/io_vic/rtl/variants
/socgen/trunk/projects/io/ip/io_vic/rtl/verilog/top.v
/socgen/trunk/projects/io/ip/io_vic/rtl/xml/io_vic.xml
/socgen/trunk/projects/io/ip/io_vic/sim/log
/socgen/trunk/projects/logic/children
/socgen/trunk/projects/logic/ip/disp_io/rtl/variants
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/disp_io/rtl/xml/disp_io.xml
/socgen/trunk/projects/logic/ip/disp_io/sim/log
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/variants
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
/socgen/trunk/projects/logic/ip/flash_memcontrl/sim/log
/socgen/trunk/projects/logic/ip/micro_bus/rtl/variants
/socgen/trunk/projects/logic/ip/micro_bus/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/micro_bus/rtl/xml/micro_bus.xml
/socgen/trunk/projects/logic/ip/micro_bus/sim/log
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/variants
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/fsm.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
/socgen/trunk/projects/logic/ip/ps2_interface/sim/log
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/variants
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
/socgen/trunk/projects/logic/ip/serial_rcvr/sim/log
/socgen/trunk/projects/logic/ip/uart/rtl/variants
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/uart/rtl/xml/uart.xml
/socgen/trunk/projects/logic/ip/uart/sim/log
/socgen/trunk/projects/logic/ip/usb_epp/rtl/variants
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml
/socgen/trunk/projects/logic/ip/usb_epp/sim/log
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl/defines.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl_600x432/defines.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_display.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_gen.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/svga_timing_generation.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/video_out.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml
/socgen/trunk/projects/logic/ip/vga_char_ctrl/sim/log
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/variants
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
/socgen/trunk/projects/Mos6502/ip/T6502/sim/log
/socgen/trunk/projects/Mos6502/ip/T6502/sim/run/inst_2_test/wave.sav
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/variants/T6502_cpu
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/alu
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/alu_logic
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/control
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/defines
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/inst_decode
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/sequencer
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/state_fsm
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top.v
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu/sim/log
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/variants
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/verilog/top.v
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic.xml
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/log
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_control
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_inst_decode
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_sequencer
/socgen/trunk/projects/Mos6502/ip/T6502_cpu_state_fsm
/socgen/trunk/projects/Mos6502/sw/tim_1/ok_no_jsr
/socgen/trunk/projects/Mos6502/sw/tim_1/tim_1.asm.xxx
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
/socgen/trunk/projects/pic_micro/ip/mrisc/sim/log
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/variants
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/alu.v
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/fifo.v
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/presclr_wdt.v
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/register_file.v
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.v
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu.xml
/socgen/trunk/projects/pic_micro/ip/mrisc_cpu/sim/log
/socgen/trunk/projects/pic_micro/ip/soc/rtl/xml/soc_mrisc_io.xml
/socgen/trunk/tools/bin/build_cmp
/socgen/trunk/tools/bin/build_leaf
/socgen/trunk/tools/bin/Makefile.root
/socgen/trunk/tools/bin/soc_builder
/socgen/trunk/tools/bin/soc_link

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