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[/] [socgen/] [trunk/] [tools/] - Rev 100

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Last modification

  • Rev 100, 2011-11-29 19:54:34 GMT
  • Author: jt_eaton
  • Log message:
    created workspace prroject=fpga_mrisc for single compile
    general cleanup
Path
/socgen/trunk/Makefile
/socgen/trunk/projects/Busdefs
/socgen/trunk/projects/cde
/socgen/trunk/projects/fpgas
/socgen/trunk/projects/io
/socgen/trunk/projects/logic
/socgen/trunk/projects/Mos6502
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone/soc
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc
/socgen/trunk/projects/opencores.org/fpga_mrisc/bin
/socgen/trunk/projects/opencores.org/fpga_mrisc/bin/Makefile.6502
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/bin
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/doc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/doc/copyright.v
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/doc/html
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/doc/png
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/doc/timing
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/ip-xact
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/verilog
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/verilog/top.jabc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/verilog/top.ps2
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/verilog/top.uart
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/verilog/top.vga
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/bin
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/icarus
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/icarus/loop
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/icarus/loop/dmp_define
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/icarus/loop/test_define
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/icarus/loop/wave.sav
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/sim/xml/Basys_mrisc_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/soc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/syn
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/syn/ise
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/syn/ise/Basys_mrisc_loop
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/syn/ise/Basys_mrisc_loop/bsdl
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_mrisc/syn/ise/Basys_mrisc_loop/bsdl/xc3s100e_vq100_1532.bsd
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/bin
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/doc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/doc/copyright.v
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/doc/html
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/doc/png
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/doc/timing
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/ip-xact
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/verilog
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/verilog/top.jabc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/verilog/top.mdisp
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/verilog/top.vga
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/bin
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/icarus
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/icarus/mouse
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/icarus/mouse/dmp_define
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/icarus/mouse/test_define
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/icarus/mouse/wave.sav
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/soc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/syn
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/syn/ise
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/syn/ise/Basys_soc_mrisc_io_mouse_mouse
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/syn/ise/Basys_soc_mrisc_io_mouse_mouse/bsdl
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Basys_soc_mrisc/syn/ise/Basys_soc_mrisc_io_mouse_mouse/bsdl/xc3s100e_vq100_1532.bsd
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/bin
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/copyright.v
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/html
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/orig6502.txt
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/png
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/Readme.txt
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/spec.odt
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/T6502_doc.txt
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/doc/timing
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/ip-xact
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/verilog
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/verilog/top.disp_1
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/verilog/top.ext
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/verilog/top.jabc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/verilog/top.rs_uart
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/verilog/top.vga
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_default.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/bin
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/icarus
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/icarus/io_mouse_mouse
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/icarus/io_mouse_mouse/dmp_define
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/icarus/io_mouse_mouse/test_define
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/icarus/io_mouse_mouse/wave.sav
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_tb.xml
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/soc
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/syn
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/syn/ise
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/syn/ise/Nexys2_soc_mrisc_io_mouse_mouse
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/syn/ise/Nexys2_soc_mrisc_io_mouse_mouse/bsdl
/socgen/trunk/projects/opencores.org/fpga_mrisc/ip/Nexys2_soc_mrisc/syn/ise/Nexys2_soc_mrisc_io_mouse_mouse/bsdl/xc3s1200e_fg320_1532.bsd
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/font
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/font/font.asm
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/font/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/startup
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/startup/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/startup/startup.asm
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/vga_font
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/vga_font/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/vga_font/vga_font.asm
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/vga_startup_screen
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/vga_startup_screen/Makefile
/socgen/trunk/projects/opencores.org/fpga_mrisc/sw/vga_startup_screen/vga_startup_screen.asm
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
/socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_module/sim/xml/io_module_tb.xml
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/verilog/top.body
/socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic.xml
/socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/verilog/top.body
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/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/doc/html
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/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/doc/README.txt
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/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/bin
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/icarus
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/icarus/mouse_mrisc
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/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/xml
/socgen/trunk/projects/opencores.org/pic_micro/ip/soc_mrisc/sim/xml/soc_mrisc_io_tb.xml
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/socgen/trunk/projects/pic_micro
/socgen/trunk/projects/targets
/socgen/trunk/projects/Testbench
/socgen/trunk/tools/bin/Makefile.root
/socgen/trunk/tools/install/Ubuntu_11.10
/socgen/trunk/tools/install/Ubuntu_11.10/Makefile
/socgen/trunk/tools/install/Ubuntu_11.10/README.txt
/socgen/trunk/tools/Jtag_programmers/etc/udev/rules.d/xusbdfwu.rules
/socgen/trunk/tools/Jtag_programmers/Makefile
/socgen/trunk/tools/sys/build_registers
/socgen/trunk/tools/sys/build_sim_filelists
/socgen/trunk/tools/sys/build_verilog
/socgen/trunk/tools/sys/build_verilogLibraryFile
/socgen/trunk/tools/sys/soc_builder
/socgen/trunk/tools/sys/soc_document
/socgen/trunk/tools/sys/soc_generate
/socgen/trunk/tools/sys/workspace

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