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[/] [socgen/] [trunk/] [tools/] - Rev 113

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Last modification

Rev 113, 2012-04-11 04:36:03 GMT
Author: jt_eaton
Log message:
started refactoring or1200

Path
/socgen/trunk/Makefile
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/sim/cde_sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/verilog/syn/cde_sram_be.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_be.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram/rtl/xml/cde_sram_dp.xml
/socgen/trunk/projects/opencores.org/or1k/bin/compile
/socgen/trunk/projects/opencores.org/or1k/bin/Makefile.or32
/socgen/trunk/projects/opencores.org/or1k/doc
/socgen/trunk/projects/opencores.org/or1k/doc/pdf
/socgen/trunk/projects/opencores.org/or1k/doc/pdf/case_or1k.pdf
/socgen/trunk/projects/opencores.org/or1k/doc/pdf/journal.pdf
/socgen/trunk/projects/opencores.org/or1k/doc/src
/socgen/trunk/projects/opencores.org/or1k/doc/src/case_or1k.html
/socgen/trunk/projects/opencores.org/or1k/doc/src/drawing
/socgen/trunk/projects/opencores.org/or1k/doc/src/drawing/sch
/socgen/trunk/projects/opencores.org/or1k/doc/src/drawing/sym
/socgen/trunk/projects/opencores.org/or1k/doc/src/journal.html
/socgen/trunk/projects/opencores.org/or1k/doc/src/openrisc_arch_draft.odt
/socgen/trunk/projects/opencores.org/or1k/doc/src/png
/socgen/trunk/projects/opencores.org/or1k/doc/src/slides
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/or1200_dbg.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/ip-xact/or1200_dbg_tb.designCfg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_defines.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_dpram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_dpram_256x32.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_monitor_defines.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_spram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_spram_32_bw.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/or1200_tpram_32x32.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/synthesys
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/top.or1200_mon
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/verilog/wb_checker.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.design.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/rtl/xml/or1200_dbg.xml
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/bin/Makefile
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic_sprs_tt
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic_sprs_tt/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic_sprs_tt/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-basic_sprs_tt/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cbasic
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cbasic/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cbasic/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cbasic/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cy
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cy/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cy/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-cy/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dctest
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dctest/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dctest/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-dctest/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-div/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-ext/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-ffl1/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-ffl1/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-ffl1/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-float
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-float/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-float/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-float/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-fp/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-fp/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mac
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mac/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mac/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mac/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-maci/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-mul/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-no_code_sprs_sys/wave.sav
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-ov
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-ov/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-qmem/dmp_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-qmem/test_define
/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/icarus/or1200-qmem/wave.sav
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/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_ram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_dc_tag.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_fsm.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_ram.v
/socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/verilog/or1200_ic_tag.v
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