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[/] [socgen/] [trunk/] [tools/] - Rev 46

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Last modification

  • Rev 46, 2010-08-11 16:04:09 GMT
  • Author: jt_eaton
  • Log message:
    removed hard coded component names from design files
    define file is always defines.v
    top level is always top.v
Path
/socgen/trunk/Makefile
/socgen/trunk/projects/logic/ip/disp_io/rtl/variants/disp_io/defines.v
/socgen/trunk/projects/logic/ip/disp_io/rtl/variants/disp_io/disp_io_defines.v
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/disp_io.v
/socgen/trunk/projects/logic/ip/disp_io/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/variants/flash_memcontrl/defines.v
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/variants/flash_memcontrl/flash_memcontrl_defines.v
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/flash_memcontrl.v
/socgen/trunk/projects/logic/ip/flash_memcontrl/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/io_module/rtl/variants/io_module/defines.v
/socgen/trunk/projects/logic/ip/io_module/rtl/variants/io_module/io_module_defines.v
/socgen/trunk/projects/logic/ip/io_module/rtl/variants/io_module_mouse/defines.v
/socgen/trunk/projects/logic/ip/io_module/rtl/variants/io_module_mouse/io_module_defines.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/gpio_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_gpio.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_gpio_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_mem.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_pic.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_pic_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_ps2.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_ps2_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_timer.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_timer_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_uart.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_uart_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_utimer.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_utimer_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_vga.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_vga_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/mem.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/pic.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/pic_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/ps2.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/ps2_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/timer.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/timer_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/uart.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/uart_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/utimer.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/utimer_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/vga.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/vga_micro_reg.v
/socgen/trunk/projects/logic/ip/io_module/rtl/verilog/vic.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/variants/ps2_interface/defines.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/variants/ps2_interface/ps2_interface_defines.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/fsm.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface_fsm.v
/socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/variants/serial_rcvr/defines.v
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/variants/serial_rcvr/serial_rcvr_defines.v
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/serial_rcvr.v
/socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/uart/rtl/variants/uart/defines.v
/socgen/trunk/projects/logic/ip/uart/rtl/variants/uart/uart_defines.v
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/uart/rtl/verilog/uart.v
/socgen/trunk/projects/logic/ip/usb_epp/rtl/variants/usb_epp/defines.v
/socgen/trunk/projects/logic/ip/usb_epp/rtl/variants/usb_epp/usb_epp_defines.v
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/usb_epp/rtl/verilog/usb_epp.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl/defines.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl/vga_char_ctrl_defines.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl_600x432/defines.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl_600x432/vga_char_ctrl_defines.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_display.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_gen.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/svga_timing_generation.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/top.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_char_display.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_char_gen.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_svga_timing_generation.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_video_out.v
/socgen/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/video_out.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/variants/T6502/defines.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/variants/T6502/T6502_defines.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/alu.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/alu_ctrl.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/control.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/core.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/inst_decode.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/sequencer.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/state_fsm.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_alu.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_alu_ctrl.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_control.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_core.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_inst_decode.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_sequencer.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_state_fsm.v
/socgen/trunk/projects/Mos6502/ip/T6502/rtl/verilog/top.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/variants/mrisc/defines.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/variants/mrisc/mrisc_defines.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/alu.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/fifo.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_alu.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_fifo.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_presclr_wdt.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_register_file.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/presclr_wdt.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/register_file.v
/socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/top.v
/socgen/trunk/projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse_mrisc/defines.v
/socgen/trunk/projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse_mrisc/soc_mouse_defines.v
/socgen/trunk/projects/pic_micro/ip/soc_mouse/rtl/verilog/soc_mouse.v
/socgen/trunk/projects/pic_micro/ip/soc_mouse/rtl/verilog/top.v
/socgen/trunk/tools/bin/Makefile.root
/socgen/trunk/tools/bin/Makefile.root.x11

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