OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [documentation/] - Rev 128

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Last modification

  • Rev 128, 2013-09-14 20:11:45 GMT
  • Author: jt_eaton
  • Log message:
    major cleanup
    added toolflows for sim,syn,documentation,linting and verilog
    added documentation tools
Path
/socgen/trunk/doc/src/guides/reset_sys_design.html
/socgen/trunk/Makefile
/socgen/trunk/make_doc
/socgen/trunk/projects/digilentinc.com/Nexys2/doc
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/bin
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/bin/Makefile
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/ip-xact
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/verilog
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/verilog/syn
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/verilog/syn/clock_sys.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_core.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/bin
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/bin/Makefile
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/ip-xact
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl/verilog
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl/verilog/syn
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl/verilog/syn/jtag_tap.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl/xml/cde_jtag_tap.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/verilog
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/verilog/pad_in_dig.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/verilog/pad_od_dig.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/verilog/pad_out_dig.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/verilog/pad_se_dig.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/verilog/pad_tri_dig.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_tri_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint/sram_be.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint/sram_def.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint/sram_dp.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/sram_be.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/sram_def.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/sram_dp.v
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_be.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_def.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_dp.xml
/socgen/trunk/projects/github.com/mor1kx
/socgen/trunk/projects/github.com/openrisc
/socgen/trunk/projects/github.com/openrisc/bin
/socgen/trunk/projects/github.com/openrisc/bin/compile
/socgen/trunk/projects/github.com/openrisc/bin/Makefile.or32
/socgen/trunk/projects/github.com/openrisc/bin/repeater
/socgen/trunk/projects/github.com/openrisc/doc
/socgen/trunk/projects/github.com/openrisc/doc/html
/socgen/trunk/projects/github.com/openrisc/doc/html/mor1kx_cappuccino.html
/socgen/trunk/projects/github.com/openrisc/doc/html/mor1kx_espresso.html
/socgen/trunk/projects/github.com/openrisc/doc/html/mor1kx_prontoespresso.html
/socgen/trunk/projects/github.com/openrisc/ip-xact
/socgen/trunk/projects/github.com/openrisc/ip-xact/libraryCfg.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx
/socgen/trunk/projects/github.com/openrisc/mor1kx/componentCfg.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/doc
/socgen/trunk/projects/github.com/openrisc/mor1kx/doc/docbook-xsl.css
/socgen/trunk/projects/github.com/openrisc/mor1kx/doc/docbook.xsl
/socgen/trunk/projects/github.com/openrisc/mor1kx/doc/gen-docinfo.pl
/socgen/trunk/projects/github.com/openrisc/mor1kx/doc/Makefile
/socgen/trunk/projects/github.com/openrisc/mor1kx/doc/mor1kx.asciidoc
/socgen/trunk/projects/github.com/openrisc/mor1kx/LICENSE
/socgen/trunk/projects/github.com/openrisc/mor1kx/README.pod
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx-defines.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx-sprs.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_branch_prediction.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_bus_if_wb32.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_cfgrs.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_core
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_cpu.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_cpu_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_cpu_espresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_cpu_prontoespresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_ctrl_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_ctrl_espresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_ctrl_prontoespresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_dcache.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_decode.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_decode_execute_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_dmmu.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_execute_alu.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_fetch_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_fetch_espresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_fetch_prontoespresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_icache.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_immu.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_lsu_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_lsu_espresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_pic.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_rf_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_rf_espresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_rf_ram.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_simple_dpram_sclk.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_ticktimer.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_true_dpram_sclk.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_wb_mux_cappuccino.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/mor1kx_wb_mux_espresso.v
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/verilog/SYNTHESIS
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/xml/mor1kx_cappuccino.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/xml/mor1kx_def.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/xml/mor1kx_espresso.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/rtl/xml/mor1kx_prontoespresso.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/bin
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/bin/Makefile
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic/dmp_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic/test_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic/wave.sav
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_cap
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_cap/dmp_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_cap/test_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_cap/wave.sav
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_esp
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_esp/dmp_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_esp/test_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_esp/wave.sav
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_pro
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_pro/dmp_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_pro/test_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-basic_pro/wave.sav
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-cbasic
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-cbasic/dmp_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-cbasic/test_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/icarus/or1200-cbasic/wave.sav
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/verilog
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/verilog/top.rtl
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/verilog/top.vtb
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_bfm.design.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_cappuccino_dut.params.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_cappuccino_dutg.design.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_cappuccino_lint.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_cappuccino_tb.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_def_dut.params.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_def_dutg.design.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_def_tb.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_def_vtb.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_espresso_dut.params.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_espresso_dutg.design.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_espresso_lint.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_espresso_tb.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_prontoespresso_dut.params.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_prontoespresso_dutg.design.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_prontoespresso_lint.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/testbenches/xml/mor1kx_prontoespresso_tb.xml
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/verilator
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/verilator/or1200-basic
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/verilator/or1200-basic/test_define
/socgen/trunk/projects/github.com/openrisc/mor1kx/sim/verilator/or1200-basic/wave.sav
/socgen/trunk/projects/github.com/openrisc/sw
/socgen/trunk/projects/github.com/openrisc/sw/backend
/socgen/trunk/projects/github.com/openrisc/sw/backend/board.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/cpu-utils.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/int.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/lib-utils.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/link.ld
/socgen/trunk/projects/github.com/openrisc/sw/backend/or1200-defines.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/or1200-utils.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/orpsoc-defines.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/printf.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/spr-defs.h
/socgen/trunk/projects/github.com/openrisc/sw/backend/uart.h
/socgen/trunk/projects/github.com/openrisc/sw/cache
/socgen/trunk/projects/github.com/openrisc/sw/cache/cache.S
/socgen/trunk/projects/github.com/openrisc/sw/cache/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/crt0
/socgen/trunk/projects/github.com/openrisc/sw/crt0/crt0.S
/socgen/trunk/projects/github.com/openrisc/sw/crt0/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/exceptions
/socgen/trunk/projects/github.com/openrisc/sw/exceptions/exceptions.c
/socgen/trunk/projects/github.com/openrisc/sw/exceptions/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/int
/socgen/trunk/projects/github.com/openrisc/sw/int/int.c
/socgen/trunk/projects/github.com/openrisc/sw/int/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/intgen-intsyscall
/socgen/trunk/projects/github.com/openrisc/sw/intgen-intsyscall/intgen-intsyscall.S
/socgen/trunk/projects/github.com/openrisc/sw/intgen-intsyscall/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/intgen-ticksyscall
/socgen/trunk/projects/github.com/openrisc/sw/intgen-ticksyscall/intgen-ticksyscall.S
/socgen/trunk/projects/github.com/openrisc/sw/intgen-ticksyscall/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/lib-utils
/socgen/trunk/projects/github.com/openrisc/sw/lib-utils/lib-utils.c
/socgen/trunk/projects/github.com/openrisc/sw/lib-utils/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/liborpsoc
/socgen/trunk/projects/github.com/openrisc/sw/liborpsoc/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/mmu
/socgen/trunk/projects/github.com/openrisc/sw/mmu/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/mmu/mmu.S
/socgen/trunk/projects/github.com/openrisc/sw/or1200-basic
/socgen/trunk/projects/github.com/openrisc/sw/or1200-basic/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/or1200-basic/or1200-basic.S
/socgen/trunk/projects/github.com/openrisc/sw/or1200-cbasic
/socgen/trunk/projects/github.com/openrisc/sw/or1200-cbasic/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/or1200-cbasic/or1200-cbasic.c
/socgen/trunk/projects/github.com/openrisc/sw/or1200-cy
/socgen/trunk/projects/github.com/openrisc/sw/or1200-cy/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/or1200-cy/or1200-cy.S
/socgen/trunk/projects/github.com/openrisc/sw/or1200-dctest
/socgen/trunk/projects/github.com/openrisc/sw/or1200-dctest/Makefile
/socgen/trunk/projects/github.com/openrisc/sw/or1200-dctest/or1200-dctest.c
/socgen/trunk/projects/github.com/openrisc/sw/or1200-div
/socgen/trunk/projects/github.com/openrisc/sw/or1200-div/Makefile
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