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[/] [socgen/] [trunk/] [tools/] [sys/] - Rev 99

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Last modification

  • Rev 99, 2011-10-18 03:18:00 GMT
  • Author: jt_eaton
  • Log message:
    moved all projects into /projects/opencores.org
    added build_register
    added fizzim
Path
/socgen/trunk/doc/src/drawing/sch/data_fig1.sch
/socgen/trunk/Makefile
/socgen/trunk/projects/Busdefs/ip/clock/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/clock/busdeftypes/clock.xml
/socgen/trunk/projects/Busdefs/ip/clock/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/clock/rtl/xml/clock.xml
/socgen/trunk/projects/Busdefs/ip/clock/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/clock/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/enable/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/enable/busdeftypes/enable.xml
/socgen/trunk/projects/Busdefs/ip/enable/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/enable/rtl/xml/enable.xml
/socgen/trunk/projects/Busdefs/ip/enable/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/enable/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/ext_bus/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/ext_bus/busdeftypes/micro_bus.xml
/socgen/trunk/projects/Busdefs/ip/ext_bus/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/ext_bus/rtl/xml/ext_bus.xml
/socgen/trunk/projects/Busdefs/ip/ext_bus/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/ext_bus/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/jtag/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/jtag/busdeftypes/jtag.xml
/socgen/trunk/projects/Busdefs/ip/jtag/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/jtag/rtl/xml/jtag_rpc.xml
/socgen/trunk/projects/Busdefs/ip/jtag/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/jtag/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/micro_bus/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/micro_bus/busdeftypes/micro_bus.xml
/socgen/trunk/projects/Busdefs/ip/micro_bus/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/micro_bus/rtl/xml/micro_bus.xml
/socgen/trunk/projects/Busdefs/ip/micro_bus/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/micro_bus/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/pad/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/pad/busdeftypes/pad.xml
/socgen/trunk/projects/Busdefs/ip/pad/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/pad/rtl/xml/pad.xml
/socgen/trunk/projects/Busdefs/ip/pad/rtl/xml/pad_mux.xml
/socgen/trunk/projects/Busdefs/ip/pad/rtl/xml/pad_ring.xml
/socgen/trunk/projects/Busdefs/ip/pad/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/pad/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/ps2/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/ps2/busdeftypes/ps2.xml
/socgen/trunk/projects/Busdefs/ip/ps2/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/ps2/rtl/xml/ps2.xml
/socgen/trunk/projects/Busdefs/ip/ps2/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/ps2/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/reset/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/reset/busdeftypes/reset.xml
/socgen/trunk/projects/Busdefs/ip/reset/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/reset/rtl/xml/reset.xml
/socgen/trunk/projects/Busdefs/ip/reset/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/reset/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/uart/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/uart/busdeftypes/uart.xml
/socgen/trunk/projects/Busdefs/ip/uart/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/uart/rtl/xml/uart.xml
/socgen/trunk/projects/Busdefs/ip/uart/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/uart/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/vga/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/vga/busdeftypes/vga.xml
/socgen/trunk/projects/Busdefs/ip/vga/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/vga/rtl/xml/vga.xml
/socgen/trunk/projects/Busdefs/ip/vga/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/vga/soc/design.soc
/socgen/trunk/projects/Busdefs/ip/wishbone/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/wishbone/busdeftypes/wishbone.xml
/socgen/trunk/projects/Busdefs/ip/wishbone/doc/copyright.v
/socgen/trunk/projects/Busdefs/ip/wishbone/rtl/xml/wishbone.xml
/socgen/trunk/projects/Busdefs/ip/wishbone/sim/bin/Makefile
/socgen/trunk/projects/Busdefs/ip/wishbone/soc/design.soc
/socgen/trunk/projects/Busdefs/soc/library.soc
/socgen/trunk/projects/cde/bin/repeater
/socgen/trunk/projects/cde/doc/drawing/sym/cde_asyncdisable.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_clk_diff_testmux.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_clk_gater.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_clk_testmux.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_clock_sys.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_clock_sys_mult.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_divider.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_jtag.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_jtag_rpc_reg.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_lifo.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_pad_se_dig.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_reset.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_serial_rcvr.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_serial_xmit.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_sram.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_sync.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_sync_with_hysteresis.sym
/socgen/trunk/projects/cde/doc/drawing/sym/cde_sync_with_reset.sym
/socgen/trunk/projects/cde/doc/html/blocks.html
/socgen/trunk/projects/cde/doc/html/cde_asyncdisable.html
/socgen/trunk/projects/cde/doc/html/cde_clk_diff_testmux.html
/socgen/trunk/projects/cde/doc/html/cde_clk_gater.html
/socgen/trunk/projects/cde/doc/html/cde_clk_testmux.html
/socgen/trunk/projects/cde/doc/html/cde_clock_sys.html
/socgen/trunk/projects/cde/doc/html/cde_dft.html
/socgen/trunk/projects/cde/doc/html/cde_divider.html
/socgen/trunk/projects/cde/doc/html/cde_jtag.html
/socgen/trunk/projects/cde/doc/html/cde_jtag_rpc_reg.html
/socgen/trunk/projects/cde/doc/html/cde_lifo.html
/socgen/trunk/projects/cde/doc/html/cde_pad_se_dig.html
/socgen/trunk/projects/cde/doc/html/cde_reset.html
/socgen/trunk/projects/cde/doc/html/cde_serial_rcvr.html
/socgen/trunk/projects/cde/doc/html/cde_serial_xmit.html
/socgen/trunk/projects/cde/doc/html/cde_sram.html
/socgen/trunk/projects/cde/doc/html/cde_sync.html
/socgen/trunk/projects/cde/doc/html/cde_synchronizers.html
/socgen/trunk/projects/cde/doc/html/cde_sync_with_hysteresis.html
/socgen/trunk/projects/cde/doc/html/cde_sync_with_reset.html
/socgen/trunk/projects/cde/doc/html/jtag.html
/socgen/trunk/projects/cde/doc/html/pads.html
/socgen/trunk/projects/cde/doc/html/srams.html
/socgen/trunk/projects/cde/doc/index.html
/socgen/trunk/projects/cde/doc/pdf/cde_sram.pdf
/socgen/trunk/projects/cde/doc/png/cde_asyncdisable.png
/socgen/trunk/projects/cde/doc/png/cde_clk_diff_testmux.png
/socgen/trunk/projects/cde/doc/png/cde_clk_gater.png
/socgen/trunk/projects/cde/doc/png/cde_clk_testmux.png
/socgen/trunk/projects/cde/doc/png/cde_clock_sys.png
/socgen/trunk/projects/cde/doc/png/cde_divider.png
/socgen/trunk/projects/cde/doc/png/cde_jtag.png
/socgen/trunk/projects/cde/doc/png/cde_jtag_rpc_reg.png
/socgen/trunk/projects/cde/doc/png/cde_lifo.png
/socgen/trunk/projects/cde/doc/png/cde_pad_se_dig.png
/socgen/trunk/projects/cde/doc/png/cde_reset.png
/socgen/trunk/projects/cde/doc/png/cde_serial_rcvr.png
/socgen/trunk/projects/cde/doc/png/cde_serial_xmit.png
/socgen/trunk/projects/cde/doc/png/cde_sram.png
/socgen/trunk/projects/cde/doc/png/cde_sync.png
/socgen/trunk/projects/cde/doc/png/cde_sync_with_hysteresis.png
/socgen/trunk/projects/cde/doc/png/cde_sync_with_reset.png
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_diff_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_gater.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_multiplier.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_sys.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/sim/cde_clock_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_diff_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_gater.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_multiplier.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_sys.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/verilog/syn/cde_clock_testmux.v
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_multiplier.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/cde/ip/cde_clock/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_divider/rtl/verilog/sim/cde_divider.v
/socgen/trunk/projects/cde/ip/cde_divider/rtl/verilog/syn/cde_divider.v
/socgen/trunk/projects/cde/ip/cde_divider/rtl/xml/cde_divider.xml
/socgen/trunk/projects/cde/ip/cde_divider/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/verilog/sim/cde_fifo.v
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/verilog/syn/cde_fifo.v
/socgen/trunk/projects/cde/ip/cde_fifo/rtl/xml/cde_fifo.xml
/socgen/trunk/projects/cde/ip/cde_fifo/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/verilog/sim/cde_io_mux.v
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/verilog/syn/cde_io_mux.v
/socgen/trunk/projects/cde/ip/cde_io_mux/rtl/xml/cde_io_mux.xml
/socgen/trunk/projects/cde/ip/cde_io_mux/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_jtag/bin/Makefile
/socgen/trunk/projects/cde/ip/cde_jtag/doc/copyright.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/sim/cde_jtag_classic_rpc_in_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/sim/cde_jtag_classic_rpc_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/sim/cde_jtag_rpc_in_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/sim/cde_jtag_rpc_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/syn/cde_jtag_classic_rpc_in_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/syn/cde_jtag_classic_rpc_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/syn/cde_jtag_rpc_in_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/gen/syn/cde_jtag_rpc_reg.v
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.body
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.bsr
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.instr_reg
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.sim
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.tap
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/verilog/top.tdo
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag.xml
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
/socgen/trunk/projects/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.xml
/socgen/trunk/projects/cde/ip/cde_jtag/sim/bin/Makefile
/socgen/trunk/projects/cde/ip/cde_jtag/sim/icarus/default/dmp_define
/socgen/trunk/projects/cde/ip/cde_jtag/sim/icarus/default/test_define
/socgen/trunk/projects/cde/ip/cde_jtag/sim/icarus/default/wave.sav
/socgen/trunk/projects/cde/ip/cde_jtag/sim/xml/cde_jtag_tb.xml
/socgen/trunk/projects/cde/ip/cde_jtag/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/verilog/sim/cde_lifo.v
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/verilog/syn/cde_lifo.v
/socgen/trunk/projects/cde/ip/cde_lifo/rtl/xml/cde_lifo.xml
/socgen/trunk/projects/cde/ip/cde_lifo/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_diff_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_in_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_od_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_out_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/sim/cde_pad_se_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_diff_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_in_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_od_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_out_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/verilog/syn/cde_pad_se_dig.v
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_diff_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/cde/ip/cde_pad/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/verilog/sim/cde_prescale.v
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/verilog/syn/cde_prescale.v
/socgen/trunk/projects/cde/ip/cde_prescale/rtl/xml/cde_prescale.xml
/socgen/trunk/projects/cde/ip/cde_prescale/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/sim/cde_reset.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/sim/cde_reset_asyncdisable.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/syn/cde_reset.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/verilog/syn/cde_reset_asyncdisable.v
/socgen/trunk/projects/cde/ip/cde_reset/rtl/xml/cde_reset.xml
/socgen/trunk/projects/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/cde/ip/cde_reset/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/sim/cde_serial_rcvr.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/sim/cde_serial_xmit.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/syn/cde_serial_rcvr.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/verilog/syn/cde_serial_xmit.v
/socgen/trunk/projects/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.xml
/socgen/trunk/projects/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.xml
/socgen/trunk/projects/cde/ip/cde_serial/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_sram/rtl/verilog/sim/cde_sram.v
/socgen/trunk/projects/cde/ip/cde_sram/rtl/verilog/syn/cde_sram.v
/socgen/trunk/projects/cde/ip/cde_sram/rtl/xml/cde_sram.xml
/socgen/trunk/projects/cde/ip/cde_sram/soc/design.soc
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/sim/cde_sync.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/sim/cde_sync_with_hysteresis.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/sim/cde_sync_with_reset.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/syn/cde_sync.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/syn/cde_sync_with_hysteresis.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/verilog/syn/cde_sync_with_reset.v
/socgen/trunk/projects/cde/ip/cde_sync/rtl/xml/cde_sync.xml
/socgen/trunk/projects/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.xml
/socgen/trunk/projects/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.xml
/socgen/trunk/projects/cde/ip/cde_sync/soc/design.soc
/socgen/trunk/projects/fpgas/bin/Makefile.6502
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/bin/Makefile
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/doc/copyright.v
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/verilog/top.jabc
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/verilog/top.ps2
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/verilog/top.uart
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/verilog/top.vga
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc_default.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/bin/Makefile
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/icarus/loop/dmp_define
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/icarus/loop/test_define
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/icarus/loop/wave.sav
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/sim/xml/Basys_mrisc_tb.xml
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/soc/design.soc
/socgen/trunk/projects/fpgas/ip/Basys_mrisc/syn/ise/Basys_mrisc_loop/bsdl/xc3s100e_vq100_1532.bsd
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/bin/Makefile
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/doc/copyright.v
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/rtl/verilog/top.jabc
/socgen/trunk/projects/fpgas/ip/Basys_soc_mrisc/rtl/verilog/top.mdisp
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