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[/] [socgen/] [trunk/] [tools/] [verilog/] - Rev 125

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Last modification

  • Rev 125, 2013-02-14 01:09:53 GMT
  • Author: jt_eaton
  • Log message:
    Added two new 6502 cores in www.6502.org

    cleaned up sogen xml files and added module name control
Path
/socgen/trunk/doc/pdf/Getting_Started.pdf
/socgen/trunk/doc/src/guides/Getting_Started.odt
/socgen/trunk/doc/src/user_manuals
/socgen/trunk/doc/src/user_manuals/um_100.odt
/socgen/trunk/Makefile
/socgen/trunk/projects/digilentinc.com/Nexys2/ip-xact/libraryCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/componentCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/Nexys2_fpga_designCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/ip-xact/Nexys2_fpga_jtag_designCfg.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_core.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_jtag_padring_dut.design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_jtag_padring_tb.params.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_padring_dut.design.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/sim/xml/fpga_padring_tb.params.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/busdeftypes/clock_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/clock/rtl/xml/clock_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/busdeftypes/enable_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/enable/rtl/xml/enable_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/busdeftypes/ext_bus.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ext_bus/rtl/xml/ext_bus_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/busdeftypes/micro_bus_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/micro_bus/rtl/xml/micro_bus_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/busdeftypes/pad_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/rtl/xml/pad_mux.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/rtl/xml/pad_ring.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/pad/rtl/xml/pad_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/busdeftypes/ps2_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/ps2/rtl/xml/ps2_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/busdeftypes/reset_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/reset/rtl/xml/reset_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/busdeftypes/uart_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/uart/rtl/xml/uart_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/busdeftypes/vga_def.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/vga/rtl/xml/vga_rtl.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip/wishbone
/socgen/trunk/projects/opencores.org/cde/doc/gafrc
/socgen/trunk/projects/opencores.org/cde/ip-xact/libraryCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/cde_clock_sys.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_diff_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_dll.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_gater.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_clock/rtl/xml/cde_clock_testmux.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/cde_divider_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/cde_divider_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/cde_divider/rtl/xml/cde_divider_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/cde_fifo_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_fifo/rtl/xml/cde_fifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/busDef/xml/jtag_rpc.busDefinition.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/busDef/xml/jtag_rpc_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_classic_rpc_in_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_classic_rpc_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_rpc_in_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/cde_jtag_rpc_reg.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_classic_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_in_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/rtl/xml/cde_jtag_rpc_reg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_bfm.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/testbenches/xml/cde_jtag_def_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_jtag/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/cde_lifo_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/cde_lifo_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_lifo/rtl/xml/cde_lifo_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_generic.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_ord_r4.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/rtl/xml/cde_mult_serial.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_bfm.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_generic_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_ord_r4_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_tb.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/testbenches/xml/cde_mult_serial_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_mult/sim/xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_pad/rtl/xml/cde_pad_tri_dig.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/verilog/cde_prescale.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/cde_prescale/rtl/xml/cde_prescale_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/cde_reset_def.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/cde_reset.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/cde_reset_asyncdisable.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_asyncdisable.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_reset/rtl/xml/cde_reset_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/cde_serial_rcvr.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/cde_serial_xmit.designCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/cde_serial_rcvr.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/cde_serial_xmit.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_rcvr.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/rtl/xml/cde_serial_xmit.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/icarus
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/icarus/both
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/icarus/both/dmp_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/icarus/both/test_define
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/icarus/both/wave.sav
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/verilog
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/verilog/both.tb
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_both_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_both_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_both_tb.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_rcvr_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_rcvr_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_rcvr_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_xmit_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_xmit_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_serial/sim/testbenches/xml/cde_serial_xmit_lint.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sram
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/cde_sync_def.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/cde_sync_with_hysteresis.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/cde_sync_with_reset.v
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/lint
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/sim
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/verilog/syn
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_hysteresis.xml
/socgen/trunk/projects/opencores.org/cde/ip/cde_sync/rtl/xml/cde_sync_with_reset.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram
/socgen/trunk/projects/opencores.org/cde/ip/sram/bin
/socgen/trunk/projects/opencores.org/cde/ip/sram/ip-xact
/socgen/trunk/projects/opencores.org/cde/ip/sram/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/array
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/copyright.v
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram.lint
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_be.top
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_def.top
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_dp.top
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/write
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/write.be
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_be.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_def.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_dp.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/bin
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches/xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches/xml/sram_be_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches/xml/sram_be_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches/xml/sram_def_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches/xml/sram_def_dutg.design.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches/xml/sram_dp_dut.params.xml
/socgen/trunk/projects/opencores.org/cde/ip/sram/sim/testbenches/xml/sram_dp_dutg.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip-xact/libraryCfg.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/componentCfg.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/Nexys2_T6502_core.designCfg.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/Nexys2_T6502_fpga.designCfg.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.design.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml
/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_fpga.design.xml
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