OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [tools/] [verilog/] - Rev 130

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Last modification

  • Rev 130, 2014-12-14 02:16:50 GMT
  • Author: jt_eaton
  • Log message:
    Dec 2014 major release
    trimmed out some IP
    replaced perl database with Berkeley
Path
/socgen/trunk/Makefile
/socgen/trunk/make_doc
/socgen/trunk/profile
/socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda
/socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/png
/socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/sch
/socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/src
/socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/sym
/socgen/trunk/projects/digilentinc.com/Nexys2/doc/Heda
/socgen/trunk/projects/digilentinc.com/Nexys2/doc/Heda/busDef
/socgen/trunk/projects/digilentinc.com/Nexys2/Geda
/socgen/trunk/projects/digilentinc.com/Nexys2/Geda/png
/socgen/trunk/projects/digilentinc.com/Nexys2/Geda/sch
/socgen/trunk/projects/digilentinc.com/Nexys2/Geda/src
/socgen/trunk/projects/digilentinc.com/Nexys2/Geda/sym
/socgen/trunk/projects/digilentinc.com/Nexys2/Heda
/socgen/trunk/projects/digilentinc.com/Nexys2/Heda/busDef
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/xml/cde_clock_sys.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_core.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_padring.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl/xml/cde_jtag_tap.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_in_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_od_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_out_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_se_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_tri_dig.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_be.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_def.xml
/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_dp.xml
/socgen/trunk/projects/github.com
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/componentCfg.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_cpu0.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_cpu1.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_jfifo.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_jsp.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0_jfifo.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0_jsp.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu2_jsp.html
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu0_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu0_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu1_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu1_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jfifo_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jfifo_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jsp_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jsp_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jfifo_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jfifo_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jsp_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jsp_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu2_jsp_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu2_jsp_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_sch.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_sym.png
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_cpu0.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_cpu1.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_jfifo.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_jsp.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_wb.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_wb_cpu0.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_wb_cpu0_jfifo.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_wb_cpu0_jsp.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sch/adv_dbg_if_wb_cpu2_jsp.sch
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_cpu0.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_cpu1.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_jfifo.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_jsp.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_wb.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_wb_cpu0.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_wb_cpu0_jfifo.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_wb_cpu0_jsp.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/src/adv_dbg_if_wb_cpu2_jsp.v
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_cpu0.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_cpu1.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_jfifo.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_jsp.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu0.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu0_jfifo.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu0_jsp.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu2_jsp.sym
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu0.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu0_i.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu1.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu1_i.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jfifo.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jfifo_i.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jsp.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jsp_i.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jtag_i.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0_jfifo.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0_jsp.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu2_jsp.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_i.xml
/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_bfm.design.xml
/socgen/trunk/projects/opencores.org/Busdefs/bin
/socgen/trunk/projects/opencores.org/Busdefs/clock
/socgen/trunk/projects/opencores.org/Busdefs/clock/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/clock/doc
/socgen/trunk/projects/opencores.org/Busdefs/clock/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/clock/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/clock/doc/Heda/absDef/clock_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/clock/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/clock/doc/Heda/busDef/clock_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/clock/xml
/socgen/trunk/projects/opencores.org/Busdefs/clock/xml/clock_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/clock/xml/clock_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/enable
/socgen/trunk/projects/opencores.org/Busdefs/enable/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/enable/doc
/socgen/trunk/projects/opencores.org/Busdefs/enable/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/enable/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/enable/doc/Heda/absDef/enable_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/enable/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/enable/doc/Heda/busDef/enable_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/enable/xml
/socgen/trunk/projects/opencores.org/Busdefs/enable/xml/enable_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/enable/xml/enable_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/doc
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/doc/Heda/absDef/ext_bus_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/doc/Heda/busDef/ext_bus_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/xml
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/xml/ext_bus_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/ext_bus/xml/ext_bus_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/ip
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/doc
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/doc/Heda/absDef/micro_bus_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/doc/Heda/busDef/micro_bus_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/xml
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/xml/micro_bus_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/micro_bus/xml/micro_bus_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/pad
/socgen/trunk/projects/opencores.org/Busdefs/pad/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc/Heda/absDef/pad_mux.txt
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc/Heda/absDef/pad_ring.txt
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc/Heda/absDef/pad_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/pad/doc/Heda/busDef/pad_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/pad/xml
/socgen/trunk/projects/opencores.org/Busdefs/pad/xml/pad_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/pad/xml/pad_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/pad/xml/pad_mux_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/pad/xml/pad_ring_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/ps2
/socgen/trunk/projects/opencores.org/Busdefs/ps2/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/ps2/doc
/socgen/trunk/projects/opencores.org/Busdefs/ps2/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/ps2/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/ps2/doc/Heda/absDef/ps2_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/ps2/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/ps2/doc/Heda/busDef/ps2_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/ps2/xml
/socgen/trunk/projects/opencores.org/Busdefs/ps2/xml/ps2_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/ps2/xml/ps2_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/reset
/socgen/trunk/projects/opencores.org/Busdefs/reset/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/reset/doc
/socgen/trunk/projects/opencores.org/Busdefs/reset/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/reset/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/reset/doc/Heda/absDef/reset_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/reset/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/reset/doc/Heda/busDef/reset_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/reset/xml
/socgen/trunk/projects/opencores.org/Busdefs/reset/xml/reset_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/reset/xml/reset_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/sw
/socgen/trunk/projects/opencores.org/Busdefs/uart
/socgen/trunk/projects/opencores.org/Busdefs/uart/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/uart/doc
/socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/absDef/uart_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/busDef/uart_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/uart/xml
/socgen/trunk/projects/opencores.org/Busdefs/uart/xml/uart_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/uart/xml/uart_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/vga
/socgen/trunk/projects/opencores.org/Busdefs/vga/componentCfg.xml
/socgen/trunk/projects/opencores.org/Busdefs/vga/doc
/socgen/trunk/projects/opencores.org/Busdefs/vga/doc/Heda
/socgen/trunk/projects/opencores.org/Busdefs/vga/doc/Heda/absDef
/socgen/trunk/projects/opencores.org/Busdefs/vga/doc/Heda/absDef/vga_rtl.txt
/socgen/trunk/projects/opencores.org/Busdefs/vga/doc/Heda/busDef
/socgen/trunk/projects/opencores.org/Busdefs/vga/doc/Heda/busDef/vga_def.txt
/socgen/trunk/projects/opencores.org/Busdefs/vga/xml
/socgen/trunk/projects/opencores.org/Busdefs/vga/xml/vga_def.busDefinition.xml
/socgen/trunk/projects/opencores.org/Busdefs/vga/xml/vga_def_rtl.abstractionDefinition.xml
/socgen/trunk/projects/opencores.org/cde/ip/clock/componentCfg.xml
/socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda
/socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/html
/socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/html/cde_clock_dll.html
/socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/html/cde_clock_gater.html
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